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1a8e41cd67
Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: <stable@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
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| .. | ||
| include/mach | ||
| core.h | ||
| ct-ca9x4.c | ||
| headsmp.S | ||
| Kconfig | ||
| localtimer.c | ||
| Makefile | ||
| Makefile.boot | ||
| platsmp.c | ||
| v2m.c | ||