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3a8fede115
During 11n RX reordering, if there is a hole in RX table, driver will not send packets to kernel until the rxreorder timer expires or the table is full. However, currently driver always restarts rxreorder timer when receiving a packet, which causes the timer hardly to expire. So while connected with to 11n AP in a busy environment, ping packets may get blocked for about 30 seconds. This patch fixes this timer restarting by ensuring rxreorder timer would only be restarted either timer is not set or start_win has changed. Signed-off-by: Chin-Ran Lo <crlo@marvell.com> Signed-off-by: Plus Chen <pchen@marvell.com> Signed-off-by: Marc Yang <yangyang@marvell.com> Signed-off-by: Cathy Luo <cluo@marvell.com> Signed-off-by: Avinash Patil <patila@marvell.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
86 lines
3.1 KiB
C
86 lines
3.1 KiB
C
/*
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* Marvell Wireless LAN device driver: 802.11n RX Re-ordering
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*
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* Copyright (C) 2011-2014, Marvell International Ltd.
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*
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* This software file (the "File") is distributed by Marvell International
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* Ltd. under the terms of the GNU General Public License Version 2, June 1991
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* (the "License"). You may use, redistribute and/or modify this File in
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* accordance with the terms and conditions of the License, a copy of which
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* is available by writing to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
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* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
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*
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* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
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* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
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* this warranty disclaimer.
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*/
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#ifndef _MWIFIEX_11N_RXREORDER_H_
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#define _MWIFIEX_11N_RXREORDER_H_
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#define MIN_FLUSH_TIMER_MS 50
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#define MIN_FLUSH_TIMER_15_MS 15
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#define MWIFIEX_BA_WIN_SIZE_32 32
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#define PKT_TYPE_BAR 0xE7
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#define MAX_TID_VALUE (2 << 11)
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#define TWOPOW11 (2 << 10)
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#define BLOCKACKPARAM_TID_POS 2
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#define BLOCKACKPARAM_AMSDU_SUPP_MASK 0x1
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#define BLOCKACKPARAM_WINSIZE_POS 6
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#define DELBA_TID_POS 12
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#define DELBA_INITIATOR_POS 11
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#define TYPE_DELBA_SENT 1
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#define TYPE_DELBA_RECEIVE 2
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#define IMMEDIATE_BLOCK_ACK 0x2
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#define ADDBA_RSP_STATUS_ACCEPT 0
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#define MWIFIEX_DEF_11N_RX_SEQ_NUM 0xffff
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#define BA_SETUP_MAX_PACKET_THRESHOLD 16
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#define BA_SETUP_PACKET_OFFSET 16
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enum mwifiex_rxreor_flags {
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RXREOR_FORCE_NO_DROP = 1<<0,
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RXREOR_INIT_WINDOW_SHIFT = 1<<1,
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};
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static inline void mwifiex_reset_11n_rx_seq_num(struct mwifiex_private *priv)
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{
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memset(priv->rx_seq, 0xff, sizeof(priv->rx_seq));
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}
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int mwifiex_11n_rx_reorder_pkt(struct mwifiex_private *,
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u16 seqNum,
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u16 tid, u8 *ta,
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u8 pkttype, void *payload);
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void mwifiex_del_ba_tbl(struct mwifiex_private *priv, int Tid,
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u8 *PeerMACAddr, u8 type, int initiator);
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void mwifiex_11n_ba_stream_timeout(struct mwifiex_private *priv,
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struct host_cmd_ds_11n_batimeout *event);
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int mwifiex_ret_11n_addba_resp(struct mwifiex_private *priv,
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struct host_cmd_ds_command
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*resp);
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int mwifiex_cmd_11n_delba(struct host_cmd_ds_command *cmd,
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void *data_buf);
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int mwifiex_cmd_11n_addba_rsp_gen(struct mwifiex_private *priv,
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struct host_cmd_ds_command *cmd,
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struct host_cmd_ds_11n_addba_req
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*cmd_addba_req);
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int mwifiex_cmd_11n_addba_req(struct host_cmd_ds_command *cmd,
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void *data_buf);
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void mwifiex_11n_cleanup_reorder_tbl(struct mwifiex_private *priv);
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struct mwifiex_rx_reorder_tbl *mwifiex_11n_get_rxreorder_tbl(struct
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mwifiex_private
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*priv, int tid,
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u8 *ta);
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struct mwifiex_rx_reorder_tbl *
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mwifiex_11n_get_rx_reorder_tbl(struct mwifiex_private *priv, int tid, u8 *ta);
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void mwifiex_11n_del_rx_reorder_tbl_by_ta(struct mwifiex_private *priv, u8 *ta);
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void mwifiex_update_rxreor_flags(struct mwifiex_adapter *adapter, u8 flags);
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#endif /* _MWIFIEX_11N_RXREORDER_H_ */
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