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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b0b4855099
XTFPGA SPI controller has native endian registers. Fix register acessors so that they work in big-endian configurations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
171 lines
4.0 KiB
C
171 lines
4.0 KiB
C
/*
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* Xtensa xtfpga SPI controller driver
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*
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* Copyright (c) 2014 Cadence Design Systems Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#define XTFPGA_SPI_NAME "xtfpga_spi"
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#define XTFPGA_SPI_START 0x0
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#define XTFPGA_SPI_BUSY 0x4
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#define XTFPGA_SPI_DATA 0x8
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#define BUSY_WAIT_US 100
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struct xtfpga_spi {
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struct spi_bitbang bitbang;
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void __iomem *regs;
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u32 data;
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unsigned data_sz;
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};
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static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi,
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unsigned addr, u32 val)
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{
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__raw_writel(val, spi->regs + addr);
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}
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static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,
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unsigned addr)
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{
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return __raw_readl(spi->regs + addr);
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}
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static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)
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{
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unsigned i;
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for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) &&
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i < BUSY_WAIT_US; ++i)
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udelay(1);
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WARN_ON_ONCE(i == BUSY_WAIT_US);
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}
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static u32 xtfpga_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
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u32 v, u8 bits)
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{
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struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
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xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0));
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xspi->data_sz += bits;
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if (xspi->data_sz >= 16) {
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xtfpga_spi_write32(xspi, XTFPGA_SPI_DATA,
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xspi->data >> (xspi->data_sz - 16));
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xspi->data_sz -= 16;
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xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 1);
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xtfpga_spi_wait_busy(xspi);
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xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
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}
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return 0;
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}
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static void xtfpga_spi_chipselect(struct spi_device *spi, int is_on)
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{
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struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
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WARN_ON(xspi->data_sz != 0);
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xspi->data_sz = 0;
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}
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static int xtfpga_spi_probe(struct platform_device *pdev)
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{
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struct xtfpga_spi *xspi;
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struct resource *mem;
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int ret;
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struct spi_master *master;
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master = spi_alloc_master(&pdev->dev, sizeof(struct xtfpga_spi));
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if (!master)
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return -ENOMEM;
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master->flags = SPI_MASTER_NO_RX;
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
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master->bus_num = pdev->dev.id;
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master->dev.of_node = pdev->dev.of_node;
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xspi = spi_master_get_devdata(master);
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xspi->bitbang.master = master;
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xspi->bitbang.chipselect = xtfpga_spi_chipselect;
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xspi->bitbang.txrx_word[SPI_MODE_0] = xtfpga_spi_txrx_word;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!mem) {
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dev_err(&pdev->dev, "No memory resource\n");
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ret = -ENODEV;
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goto err;
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}
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xspi->regs = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(xspi->regs)) {
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ret = PTR_ERR(xspi->regs);
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goto err;
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}
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xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
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usleep_range(1000, 2000);
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if (xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY)) {
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dev_err(&pdev->dev, "Device stuck in busy state\n");
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ret = -EBUSY;
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goto err;
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}
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ret = spi_bitbang_start(&xspi->bitbang);
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if (ret < 0) {
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dev_err(&pdev->dev, "spi_bitbang_start failed\n");
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goto err;
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}
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platform_set_drvdata(pdev, master);
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return 0;
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err:
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spi_master_put(master);
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return ret;
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}
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static int xtfpga_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct xtfpga_spi *xspi = spi_master_get_devdata(master);
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spi_bitbang_stop(&xspi->bitbang);
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spi_master_put(master);
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return 0;
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}
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MODULE_ALIAS("platform:" XTFPGA_SPI_NAME);
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#ifdef CONFIG_OF
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static const struct of_device_id xtfpga_spi_of_match[] = {
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{ .compatible = "cdns,xtfpga-spi", },
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{}
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};
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MODULE_DEVICE_TABLE(of, xtfpga_spi_of_match);
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#endif
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static struct platform_driver xtfpga_spi_driver = {
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.probe = xtfpga_spi_probe,
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.remove = xtfpga_spi_remove,
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.driver = {
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.name = XTFPGA_SPI_NAME,
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.of_match_table = of_match_ptr(xtfpga_spi_of_match),
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},
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};
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module_platform_driver(xtfpga_spi_driver);
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MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
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MODULE_DESCRIPTION("xtensa xtfpga SPI driver");
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MODULE_LICENSE("GPL");
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