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4470dc9cca
psb_gtt_remove is only used in this file, and make it static to eliminate missing-prototypes compiling warning. Signed-off-by: Jiang Biao <jiang.biao2@zte.com.cn> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1477972185-24826-1-git-send-email-jiang.biao2@zte.com.cn
591 lines
16 KiB
C
591 lines
16 KiB
C
/*
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* Copyright (c) 2007, Intel Corporation.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
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* Alan Cox <alan@linux.intel.com>
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*/
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#include <drm/drmP.h>
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#include <linux/shmem_fs.h>
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#include "psb_drv.h"
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#include "blitter.h"
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/*
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* GTT resource allocator - manage page mappings in GTT space
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*/
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/**
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* psb_gtt_mask_pte - generate GTT pte entry
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* @pfn: page number to encode
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* @type: type of memory in the GTT
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*
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* Set the GTT entry for the appropriate memory type.
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*/
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static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type)
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{
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uint32_t mask = PSB_PTE_VALID;
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/* Ensure we explode rather than put an invalid low mapping of
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a high mapping page into the gtt */
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BUG_ON(pfn & ~(0xFFFFFFFF >> PAGE_SHIFT));
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if (type & PSB_MMU_CACHED_MEMORY)
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mask |= PSB_PTE_CACHED;
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if (type & PSB_MMU_RO_MEMORY)
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mask |= PSB_PTE_RO;
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if (type & PSB_MMU_WO_MEMORY)
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mask |= PSB_PTE_WO;
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return (pfn << PAGE_SHIFT) | mask;
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}
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/**
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* psb_gtt_entry - find the GTT entries for a gtt_range
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* @dev: our DRM device
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* @r: our GTT range
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*
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* Given a gtt_range object return the GTT offset of the page table
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* entries for this gtt_range
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*/
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static u32 __iomem *psb_gtt_entry(struct drm_device *dev, struct gtt_range *r)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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unsigned long offset;
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offset = r->resource.start - dev_priv->gtt_mem->start;
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return dev_priv->gtt_map + (offset >> PAGE_SHIFT);
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}
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/**
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* psb_gtt_insert - put an object into the GTT
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* @dev: our DRM device
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* @r: our GTT range
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* @resume: on resume
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*
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* Take our preallocated GTT range and insert the GEM object into
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* the GTT. This is protected via the gtt mutex which the caller
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* must hold.
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*/
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static int psb_gtt_insert(struct drm_device *dev, struct gtt_range *r,
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int resume)
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{
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u32 __iomem *gtt_slot;
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u32 pte;
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struct page **pages;
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int i;
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if (r->pages == NULL) {
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WARN_ON(1);
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return -EINVAL;
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}
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WARN_ON(r->stolen); /* refcount these maybe ? */
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gtt_slot = psb_gtt_entry(dev, r);
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pages = r->pages;
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if (!resume) {
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/* Make sure changes are visible to the GPU */
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set_pages_array_wc(pages, r->npage);
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}
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/* Write our page entries into the GTT itself */
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for (i = r->roll; i < r->npage; i++) {
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pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]),
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PSB_MMU_CACHED_MEMORY);
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iowrite32(pte, gtt_slot++);
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}
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for (i = 0; i < r->roll; i++) {
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pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]),
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PSB_MMU_CACHED_MEMORY);
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iowrite32(pte, gtt_slot++);
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}
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/* Make sure all the entries are set before we return */
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ioread32(gtt_slot - 1);
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return 0;
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}
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/**
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* psb_gtt_remove - remove an object from the GTT
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* @dev: our DRM device
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* @r: our GTT range
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*
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* Remove a preallocated GTT range from the GTT. Overwrite all the
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* page table entries with the dummy page. This is protected via the gtt
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* mutex which the caller must hold.
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*/
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static void psb_gtt_remove(struct drm_device *dev, struct gtt_range *r)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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u32 __iomem *gtt_slot;
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u32 pte;
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int i;
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WARN_ON(r->stolen);
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gtt_slot = psb_gtt_entry(dev, r);
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pte = psb_gtt_mask_pte(page_to_pfn(dev_priv->scratch_page),
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PSB_MMU_CACHED_MEMORY);
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for (i = 0; i < r->npage; i++)
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iowrite32(pte, gtt_slot++);
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ioread32(gtt_slot - 1);
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set_pages_array_wb(r->pages, r->npage);
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}
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/**
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* psb_gtt_roll - set scrolling position
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* @dev: our DRM device
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* @r: the gtt mapping we are using
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* @roll: roll offset
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*
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* Roll an existing pinned mapping by moving the pages through the GTT.
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* This allows us to implement hardware scrolling on the consoles without
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* a 2D engine
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*/
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void psb_gtt_roll(struct drm_device *dev, struct gtt_range *r, int roll)
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{
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u32 __iomem *gtt_slot;
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u32 pte;
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int i;
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if (roll >= r->npage) {
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WARN_ON(1);
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return;
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}
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r->roll = roll;
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/* Not currently in the GTT - no worry we will write the mapping at
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the right position when it gets pinned */
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if (!r->stolen && !r->in_gart)
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return;
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gtt_slot = psb_gtt_entry(dev, r);
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for (i = r->roll; i < r->npage; i++) {
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pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]),
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PSB_MMU_CACHED_MEMORY);
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iowrite32(pte, gtt_slot++);
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}
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for (i = 0; i < r->roll; i++) {
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pte = psb_gtt_mask_pte(page_to_pfn(r->pages[i]),
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PSB_MMU_CACHED_MEMORY);
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iowrite32(pte, gtt_slot++);
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}
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ioread32(gtt_slot - 1);
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}
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/**
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* psb_gtt_attach_pages - attach and pin GEM pages
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* @gt: the gtt range
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*
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* Pin and build an in kernel list of the pages that back our GEM object.
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* While we hold this the pages cannot be swapped out. This is protected
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* via the gtt mutex which the caller must hold.
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*/
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static int psb_gtt_attach_pages(struct gtt_range *gt)
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{
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struct page **pages;
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WARN_ON(gt->pages);
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pages = drm_gem_get_pages(>->gem);
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if (IS_ERR(pages))
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return PTR_ERR(pages);
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gt->npage = gt->gem.size / PAGE_SIZE;
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gt->pages = pages;
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return 0;
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}
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/**
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* psb_gtt_detach_pages - attach and pin GEM pages
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* @gt: the gtt range
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*
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* Undo the effect of psb_gtt_attach_pages. At this point the pages
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* must have been removed from the GTT as they could now be paged out
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* and move bus address. This is protected via the gtt mutex which the
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* caller must hold.
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*/
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static void psb_gtt_detach_pages(struct gtt_range *gt)
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{
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drm_gem_put_pages(>->gem, gt->pages, true, false);
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gt->pages = NULL;
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}
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/**
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* psb_gtt_pin - pin pages into the GTT
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* @gt: range to pin
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*
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* Pin a set of pages into the GTT. The pins are refcounted so that
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* multiple pins need multiple unpins to undo.
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*
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* Non GEM backed objects treat this as a no-op as they are always GTT
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* backed objects.
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*/
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int psb_gtt_pin(struct gtt_range *gt)
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{
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int ret = 0;
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struct drm_device *dev = gt->gem.dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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u32 gpu_base = dev_priv->gtt.gatt_start;
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mutex_lock(&dev_priv->gtt_mutex);
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if (gt->in_gart == 0 && gt->stolen == 0) {
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ret = psb_gtt_attach_pages(gt);
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if (ret < 0)
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goto out;
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ret = psb_gtt_insert(dev, gt, 0);
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if (ret < 0) {
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psb_gtt_detach_pages(gt);
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goto out;
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}
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psb_mmu_insert_pages(psb_mmu_get_default_pd(dev_priv->mmu),
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gt->pages, (gpu_base + gt->offset),
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gt->npage, 0, 0, PSB_MMU_CACHED_MEMORY);
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}
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gt->in_gart++;
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out:
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mutex_unlock(&dev_priv->gtt_mutex);
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return ret;
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}
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/**
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* psb_gtt_unpin - Drop a GTT pin requirement
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* @gt: range to pin
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*
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* Undoes the effect of psb_gtt_pin. On the last drop the GEM object
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* will be removed from the GTT which will also drop the page references
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* and allow the VM to clean up or page stuff.
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*
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* Non GEM backed objects treat this as a no-op as they are always GTT
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* backed objects.
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*/
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void psb_gtt_unpin(struct gtt_range *gt)
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{
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struct drm_device *dev = gt->gem.dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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u32 gpu_base = dev_priv->gtt.gatt_start;
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int ret;
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/* While holding the gtt_mutex no new blits can be initiated */
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mutex_lock(&dev_priv->gtt_mutex);
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/* Wait for any possible usage of the memory to be finished */
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ret = gma_blt_wait_idle(dev_priv);
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if (ret) {
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DRM_ERROR("Failed to idle the blitter, unpin failed!");
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goto out;
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}
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WARN_ON(!gt->in_gart);
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gt->in_gart--;
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if (gt->in_gart == 0 && gt->stolen == 0) {
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psb_mmu_remove_pages(psb_mmu_get_default_pd(dev_priv->mmu),
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(gpu_base + gt->offset), gt->npage, 0, 0);
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psb_gtt_remove(dev, gt);
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psb_gtt_detach_pages(gt);
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}
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out:
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mutex_unlock(&dev_priv->gtt_mutex);
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}
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/*
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* GTT resource allocator - allocate and manage GTT address space
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*/
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/**
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* psb_gtt_alloc_range - allocate GTT address space
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* @dev: Our DRM device
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* @len: length (bytes) of address space required
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* @name: resource name
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* @backed: resource should be backed by stolen pages
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* @align: requested alignment
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*
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* Ask the kernel core to find us a suitable range of addresses
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* to use for a GTT mapping.
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*
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* Returns a gtt_range structure describing the object, or NULL on
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* error. On successful return the resource is both allocated and marked
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* as in use.
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*/
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struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev, int len,
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const char *name, int backed, u32 align)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct gtt_range *gt;
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struct resource *r = dev_priv->gtt_mem;
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int ret;
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unsigned long start, end;
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if (backed) {
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/* The start of the GTT is the stolen pages */
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start = r->start;
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end = r->start + dev_priv->gtt.stolen_size - 1;
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} else {
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/* The rest we will use for GEM backed objects */
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start = r->start + dev_priv->gtt.stolen_size;
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end = r->end;
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}
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gt = kzalloc(sizeof(struct gtt_range), GFP_KERNEL);
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if (gt == NULL)
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return NULL;
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gt->resource.name = name;
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gt->stolen = backed;
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gt->in_gart = backed;
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gt->roll = 0;
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/* Ensure this is set for non GEM objects */
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gt->gem.dev = dev;
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ret = allocate_resource(dev_priv->gtt_mem, >->resource,
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len, start, end, align, NULL, NULL);
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if (ret == 0) {
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gt->offset = gt->resource.start - r->start;
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return gt;
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}
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kfree(gt);
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return NULL;
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}
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/**
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* psb_gtt_free_range - release GTT address space
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* @dev: our DRM device
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* @gt: a mapping created with psb_gtt_alloc_range
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*
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* Release a resource that was allocated with psb_gtt_alloc_range. If the
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* object has been pinned by mmap users we clean this up here currently.
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*/
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void psb_gtt_free_range(struct drm_device *dev, struct gtt_range *gt)
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{
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/* Undo the mmap pin if we are destroying the object */
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if (gt->mmapping) {
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psb_gtt_unpin(gt);
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gt->mmapping = 0;
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}
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WARN_ON(gt->in_gart && !gt->stolen);
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release_resource(>->resource);
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kfree(gt);
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}
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static void psb_gtt_alloc(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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init_rwsem(&dev_priv->gtt.sem);
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}
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void psb_gtt_takedown(struct drm_device *dev)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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if (dev_priv->gtt_map) {
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iounmap(dev_priv->gtt_map);
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dev_priv->gtt_map = NULL;
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}
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if (dev_priv->gtt_initialized) {
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pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
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dev_priv->gmch_ctrl);
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PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL);
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(void) PSB_RVDC32(PSB_PGETBL_CTL);
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}
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if (dev_priv->vram_addr)
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iounmap(dev_priv->gtt_map);
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}
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int psb_gtt_init(struct drm_device *dev, int resume)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
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unsigned gtt_pages;
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unsigned long stolen_size, vram_stolen_size;
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unsigned i, num_pages;
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unsigned pfn_base;
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struct psb_gtt *pg;
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int ret = 0;
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uint32_t pte;
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if (!resume) {
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mutex_init(&dev_priv->gtt_mutex);
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mutex_init(&dev_priv->mmap_mutex);
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psb_gtt_alloc(dev);
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}
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pg = &dev_priv->gtt;
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/* Enable the GTT */
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pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl);
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pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
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dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED);
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dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL);
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PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
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(void) PSB_RVDC32(PSB_PGETBL_CTL);
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/* The root resource we allocate address space from */
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dev_priv->gtt_initialized = 1;
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pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK;
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/*
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* The video mmu has a hw bug when accessing 0x0D0000000.
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* Make gatt start at 0x0e000,0000. This doesn't actually
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* matter for us but may do if the video acceleration ever
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* gets opened up.
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*/
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pg->mmu_gatt_start = 0xE0000000;
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pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE);
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gtt_pages = pci_resource_len(dev->pdev, PSB_GTT_RESOURCE)
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>> PAGE_SHIFT;
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/* CDV doesn't report this. In which case the system has 64 gtt pages */
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if (pg->gtt_start == 0 || gtt_pages == 0) {
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dev_dbg(dev->dev, "GTT PCI BAR not initialized.\n");
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gtt_pages = 64;
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pg->gtt_start = dev_priv->pge_ctl;
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}
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pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE);
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pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE)
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>> PAGE_SHIFT;
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dev_priv->gtt_mem = &dev->pdev->resource[PSB_GATT_RESOURCE];
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if (pg->gatt_pages == 0 || pg->gatt_start == 0) {
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static struct resource fudge; /* Preferably peppermint */
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/* This can occur on CDV systems. Fudge it in this case.
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We really don't care what imaginary space is being allocated
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at this point */
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dev_dbg(dev->dev, "GATT PCI BAR not initialized.\n");
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pg->gatt_start = 0x40000000;
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pg->gatt_pages = (128 * 1024 * 1024) >> PAGE_SHIFT;
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|
/* This is a little confusing but in fact the GTT is providing
|
|
a view from the GPU into memory and not vice versa. As such
|
|
this is really allocating space that is not the same as the
|
|
CPU address space on CDV */
|
|
fudge.start = 0x40000000;
|
|
fudge.end = 0x40000000 + 128 * 1024 * 1024 - 1;
|
|
fudge.name = "fudge";
|
|
fudge.flags = IORESOURCE_MEM;
|
|
dev_priv->gtt_mem = &fudge;
|
|
}
|
|
|
|
pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base);
|
|
vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base
|
|
- PAGE_SIZE;
|
|
|
|
stolen_size = vram_stolen_size;
|
|
|
|
dev_dbg(dev->dev, "Stolen memory base 0x%x, size %luK\n",
|
|
dev_priv->stolen_base, vram_stolen_size / 1024);
|
|
|
|
if (resume && (gtt_pages != pg->gtt_pages) &&
|
|
(stolen_size != pg->stolen_size)) {
|
|
dev_err(dev->dev, "GTT resume error.\n");
|
|
ret = -EINVAL;
|
|
goto out_err;
|
|
}
|
|
|
|
pg->gtt_pages = gtt_pages;
|
|
pg->stolen_size = stolen_size;
|
|
dev_priv->vram_stolen_size = vram_stolen_size;
|
|
|
|
/*
|
|
* Map the GTT and the stolen memory area
|
|
*/
|
|
if (!resume)
|
|
dev_priv->gtt_map = ioremap_nocache(pg->gtt_phys_start,
|
|
gtt_pages << PAGE_SHIFT);
|
|
if (!dev_priv->gtt_map) {
|
|
dev_err(dev->dev, "Failure to map gtt.\n");
|
|
ret = -ENOMEM;
|
|
goto out_err;
|
|
}
|
|
|
|
if (!resume)
|
|
dev_priv->vram_addr = ioremap_wc(dev_priv->stolen_base,
|
|
stolen_size);
|
|
|
|
if (!dev_priv->vram_addr) {
|
|
dev_err(dev->dev, "Failure to map stolen base.\n");
|
|
ret = -ENOMEM;
|
|
goto out_err;
|
|
}
|
|
|
|
/*
|
|
* Insert vram stolen pages into the GTT
|
|
*/
|
|
|
|
pfn_base = dev_priv->stolen_base >> PAGE_SHIFT;
|
|
num_pages = vram_stolen_size >> PAGE_SHIFT;
|
|
dev_dbg(dev->dev, "Set up %d stolen pages starting at 0x%08x, GTT offset %dK\n",
|
|
num_pages, pfn_base << PAGE_SHIFT, 0);
|
|
for (i = 0; i < num_pages; ++i) {
|
|
pte = psb_gtt_mask_pte(pfn_base + i, PSB_MMU_CACHED_MEMORY);
|
|
iowrite32(pte, dev_priv->gtt_map + i);
|
|
}
|
|
|
|
/*
|
|
* Init rest of GTT to the scratch page to avoid accidents or scribbles
|
|
*/
|
|
|
|
pfn_base = page_to_pfn(dev_priv->scratch_page);
|
|
pte = psb_gtt_mask_pte(pfn_base, PSB_MMU_CACHED_MEMORY);
|
|
for (; i < gtt_pages; ++i)
|
|
iowrite32(pte, dev_priv->gtt_map + i);
|
|
|
|
(void) ioread32(dev_priv->gtt_map + i - 1);
|
|
return 0;
|
|
|
|
out_err:
|
|
psb_gtt_takedown(dev);
|
|
return ret;
|
|
}
|
|
|
|
int psb_gtt_restore(struct drm_device *dev)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct resource *r = dev_priv->gtt_mem->child;
|
|
struct gtt_range *range;
|
|
unsigned int restored = 0, total = 0, size = 0;
|
|
|
|
/* On resume, the gtt_mutex is already initialized */
|
|
mutex_lock(&dev_priv->gtt_mutex);
|
|
psb_gtt_init(dev, 1);
|
|
|
|
while (r != NULL) {
|
|
range = container_of(r, struct gtt_range, resource);
|
|
if (range->pages) {
|
|
psb_gtt_insert(dev, range, 1);
|
|
size += range->resource.end - range->resource.start;
|
|
restored++;
|
|
}
|
|
r = r->sibling;
|
|
total++;
|
|
}
|
|
mutex_unlock(&dev_priv->gtt_mutex);
|
|
DRM_DEBUG_DRIVER("Restored %u of %u gtt ranges (%u KB)", restored,
|
|
total, (size / 1024));
|
|
|
|
return 0;
|
|
}
|