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f1014d1b79
The Hardware Page Table Walker aims to speed up TLB refill exceptions
by handling them in the hardware level instead of having a software
TLB refill handler. However, a TLB refill exception can still be
thrown in certain cases such as, synchronus exceptions, or address
translation or memory errors during the HTW operation. As a result of
which, HTW must not be considered a complete replacement for the TLB
refill software handler, but rather a fast-path for it.
For HTW to work, the PWBase register must contain the task's page
global directory address so the HTW will kick in on TLB refill
exceptions.
Due to HTW being a separate engine embedded deep in the CPU pipeline,
we need to restart the HTW everytime a PTE changes to avoid HTW
fetching a old entry from the page tables. It's also necessary to
restart the HTW on context switches to prevent it from fetching a
page from the previous process. Finally, since HTW is using the
entryhi register to write the translations to the TLB, it's necessary
to stop the HTW whenever the entryhi changes (eg for tlb probe
perations) and enable it back afterwards.
== Performance ==
The following trivial test was used to measure the performance of the
HTW. Using the same root filesystem, the following command was used
to measure the number of tlb refill handler executions with and
without (using 'nohtw' kernel parameter) HTW support. The kernel was
modified to use a scratch register as a counter for the TLB refill
exceptions.
find /usr -type f -exec ls -lh {} \;
HTW Enabled:
TLB refill exceptions: 12306
HTW Disabled:
TLB refill exceptions: 17805
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/7336/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
218 lines
5.3 KiB
C
218 lines
5.3 KiB
C
/*
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* Switch a MMU context.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
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* Copyright (C) 1999 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_MMU_CONTEXT_H
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#define _ASM_MMU_CONTEXT_H
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/slab.h>
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#include <asm/cacheflush.h>
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#include <asm/hazards.h>
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#include <asm/tlbflush.h>
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#include <asm-generic/mm_hooks.h>
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#define htw_set_pwbase(pgd) \
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do { \
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if (cpu_has_htw) { \
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write_c0_pwbase(pgd); \
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back_to_back_c0_hazard(); \
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htw_reset(); \
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} \
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} while (0)
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#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
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do { \
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extern void tlbmiss_handler_setup_pgd(unsigned long); \
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tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \
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htw_set_pwbase((unsigned long)pgd); \
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} while (0)
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#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
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#define TLBMISS_HANDLER_RESTORE() \
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write_c0_xcontext((unsigned long) smp_processor_id() << \
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SMP_CPUID_REGSHIFT)
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#define TLBMISS_HANDLER_SETUP() \
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do { \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
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TLBMISS_HANDLER_RESTORE(); \
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} while (0)
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#else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
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/*
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* For the fast tlb miss handlers, we keep a per cpu array of pointers
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* to the current pgd for each processor. Also, the proc. id is stuffed
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* into the context register.
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*/
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extern unsigned long pgd_current[];
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#define TLBMISS_HANDLER_RESTORE() \
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write_c0_context((unsigned long) smp_processor_id() << \
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SMP_CPUID_REGSHIFT)
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#define TLBMISS_HANDLER_SETUP() \
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TLBMISS_HANDLER_RESTORE(); \
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back_to_back_c0_hazard(); \
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TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
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#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define ASID_INC 0x40
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#define ASID_MASK 0xfc0
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#elif defined(CONFIG_CPU_R8000)
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#define ASID_INC 0x10
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#define ASID_MASK 0xff0
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#else /* FIXME: not correct for R6000 */
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#define ASID_INC 0x1
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#define ASID_MASK 0xff
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#endif
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#define cpu_context(cpu, mm) ((mm)->context.asid[cpu])
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#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK)
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#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/*
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* All unused by hardware upper bits will be considered
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* as a software asid extension.
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*/
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#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
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#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
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/* Normal, classic MIPS get_new_mmu_context */
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static inline void
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get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
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{
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extern void kvm_local_flush_tlb_all(void);
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unsigned long asid = asid_cache(cpu);
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if (! ((asid += ASID_INC) & ASID_MASK) ) {
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if (cpu_has_vtag_icache)
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flush_icache_all();
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#ifdef CONFIG_KVM
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kvm_local_flush_tlb_all(); /* start new asid cycle */
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#else
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local_flush_tlb_all(); /* start new asid cycle */
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#endif
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if (!asid) /* fix version if needed */
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asid = ASID_FIRST_VERSION;
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}
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cpu_context(cpu, mm) = asid_cache(cpu) = asid;
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}
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/*
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* Initialize the context related info for a new mm_struct
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* instance.
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*/
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static inline int
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init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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int i;
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for_each_possible_cpu(i)
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cpu_context(i, mm) = 0;
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return 0;
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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unsigned long flags;
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local_irq_save(flags);
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/* Check if our ASID is of an older version and thus invalid */
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if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
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get_new_mmu_context(next, cpu);
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write_c0_entryhi(cpu_asid(cpu, next));
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TLBMISS_HANDLER_SETUP_PGD(next->pgd);
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/*
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* Mark current->active_mm as not "active" anymore.
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* We don't want to mislead possible IPI tlb flush routines.
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*/
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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local_irq_restore(flags);
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}
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/*
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* Destroy context related info for an mm_struct that is about
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* to be put to rest.
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*/
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static inline void destroy_context(struct mm_struct *mm)
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{
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}
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#define deactivate_mm(tsk, mm) do { } while (0)
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/*
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* After we have set current->mm to a new value, this activates
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* the context for the new mm so we see the new mappings.
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*/
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static inline void
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activate_mm(struct mm_struct *prev, struct mm_struct *next)
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{
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unsigned long flags;
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unsigned int cpu = smp_processor_id();
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local_irq_save(flags);
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/* Unconditionally get a new ASID. */
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get_new_mmu_context(next, cpu);
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write_c0_entryhi(cpu_asid(cpu, next));
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TLBMISS_HANDLER_SETUP_PGD(next->pgd);
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/* mark mmu ownership change */
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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cpumask_set_cpu(cpu, mm_cpumask(next));
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local_irq_restore(flags);
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}
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/*
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* If mm is currently active_mm, we can't really drop it. Instead,
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* we will get a new one for it.
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*/
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static inline void
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drop_mmu_context(struct mm_struct *mm, unsigned cpu)
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{
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unsigned long flags;
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local_irq_save(flags);
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if (cpumask_test_cpu(cpu, mm_cpumask(mm))) {
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get_new_mmu_context(mm, cpu);
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write_c0_entryhi(cpu_asid(cpu, mm));
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} else {
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/* will get a new context next time */
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cpu_context(cpu, mm) = 0;
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}
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local_irq_restore(flags);
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}
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#endif /* _ASM_MMU_CONTEXT_H */
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