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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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673dd36f0d
Use the SoC infrastructure to hold the interrupt controller information (i.e., base address, default priorities, interrupt controller type, and the number of IRQs). The interrupt controller base, although initially put in the soc_info structure's intc_base field, is eventually put in the global 'davinci_intc_base' so the low-level interrupt code can access it without a dereference. These changes enable the SoC default irq priorities to be put in the SoC-specific files, and the interrupt controller to be at any base address. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
160 lines
4.2 KiB
C
160 lines
4.2 KiB
C
/*
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* Interrupt handler for DaVinci boards.
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/cputype.h>
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#include <mach/common.h>
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#include <asm/mach/irq.h>
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#define IRQ_BIT(irq) ((irq) & 0x1f)
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#define FIQ_REG0_OFFSET 0x0000
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#define FIQ_REG1_OFFSET 0x0004
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#define IRQ_REG0_OFFSET 0x0008
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#define IRQ_REG1_OFFSET 0x000C
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#define IRQ_ENT_REG0_OFFSET 0x0018
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#define IRQ_ENT_REG1_OFFSET 0x001C
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#define IRQ_INCTL_REG_OFFSET 0x0020
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#define IRQ_EABASE_REG_OFFSET 0x0024
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#define IRQ_INTPRI0_REG_OFFSET 0x0030
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#define IRQ_INTPRI7_REG_OFFSET 0x004C
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static inline unsigned int davinci_irq_readl(int offset)
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{
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return __raw_readl(davinci_intc_base + offset);
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}
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static inline void davinci_irq_writel(unsigned long value, int offset)
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{
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__raw_writel(value, davinci_intc_base + offset);
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}
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/* Disable interrupt */
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static void davinci_mask_irq(unsigned int irq)
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{
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unsigned int mask;
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u32 l;
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mask = 1 << IRQ_BIT(irq);
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if (irq > 31) {
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l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
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l &= ~mask;
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davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
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} else {
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l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
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l &= ~mask;
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davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
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}
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}
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/* Enable interrupt */
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static void davinci_unmask_irq(unsigned int irq)
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{
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unsigned int mask;
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u32 l;
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mask = 1 << IRQ_BIT(irq);
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if (irq > 31) {
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l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
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l |= mask;
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davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
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} else {
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l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
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l |= mask;
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davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
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}
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}
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/* EOI interrupt */
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static void davinci_ack_irq(unsigned int irq)
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{
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unsigned int mask;
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mask = 1 << IRQ_BIT(irq);
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if (irq > 31)
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davinci_irq_writel(mask, IRQ_REG1_OFFSET);
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else
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davinci_irq_writel(mask, IRQ_REG0_OFFSET);
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}
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static struct irq_chip davinci_irq_chip_0 = {
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.name = "AINTC",
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.ack = davinci_ack_irq,
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.mask = davinci_mask_irq,
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.unmask = davinci_unmask_irq,
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};
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/* ARM Interrupt Controller Initialization */
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void __init davinci_irq_init(void)
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{
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unsigned i;
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const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
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/* Clear all interrupt requests */
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davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
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/* Disable all interrupts */
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davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
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davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
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/* Interrupts disabled immediately, IRQ entry reflects all */
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davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
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/* we don't use the hardware vector table, just its entry addresses */
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davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
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/* Clear all interrupt requests */
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davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
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davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
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for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
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unsigned j;
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u32 pri;
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for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
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pri |= (*davinci_def_priorities & 0x07) << j;
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davinci_irq_writel(pri, i);
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}
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/* set up genirq dispatch for ARM INTC */
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for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
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set_irq_chip(i, &davinci_irq_chip_0);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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if (i != IRQ_TINT1_TINT34)
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set_irq_handler(i, handle_edge_irq);
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else
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set_irq_handler(i, handle_level_irq);
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}
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}
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