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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9b6695a8ad
A recent change requires cpu_possible_map to be initialized before
smp_sched_init() but most MIPS platforms were initializing their
processors in the prom_prepare_cpus callback of smp_prepare_cpus. The
simple fix of calling prom_prepare_cpus from one of the earlier SMP
initialization hooks doesn't work well either since IPIs may require
init_IRQ() to have completed, so bit the bullet and split
prom_prepare_cpus into two initialization functions, plat_smp_setup
which is called early from setup_arch and plat_prepare_cpus called where
prom_prepare_cpus used to be called.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
161 lines
3.6 KiB
C
161 lines
3.6 KiB
C
#include <linux/linkage.h>
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#include <linux/sched.h>
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#include <asm/pmon.h>
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#include <asm/titan_dep.h>
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extern unsigned int (*mips_hpt_read)(void);
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extern void (*mips_hpt_init)(unsigned int);
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#define LAUNCHSTACK_SIZE 256
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static __initdata DEFINE_SPINLOCK(launch_lock);
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static unsigned long secondary_sp __initdata;
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static unsigned long secondary_gp __initdata;
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static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
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__attribute__((aligned(2 * sizeof(long))));
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static void __init prom_smp_bootstrap(void)
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{
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local_irq_disable();
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while (spin_is_locked(&launch_lock));
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__asm__ __volatile__(
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" move $sp, %0 \n"
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" move $gp, %1 \n"
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" j smp_bootstrap \n"
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:
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: "r" (secondary_sp), "r" (secondary_gp));
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}
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/*
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* PMON is a fragile beast. It'll blow up once the mappings it's littering
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* right into the middle of KSEG3 are blown away so we have to grab the slave
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* core early and keep it in a waiting loop.
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*/
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void __init prom_grab_secondary(void)
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{
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spin_lock(&launch_lock);
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pmon_cpustart(1, &prom_smp_bootstrap,
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launchstack + LAUNCHSTACK_SIZE, 0);
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}
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/*
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* Detect available CPUs, populate phys_cpu_present_map before smp_init
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*
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* We don't want to start the secondary CPU yet nor do we have a nice probing
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* feature in PMON so we just assume presence of the secondary core.
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*/
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void __init plat_smp_setup(void)
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{
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int i;
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cpus_clear(phys_cpu_present_map);
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for (i = 0; i < 2; i++) {
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cpu_set(i, phys_cpu_present_map);
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__cpu_number_map[i] = i;
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__cpu_logical_map[i] = i;
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}
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}
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void __init plat_prepare_cpus(unsigned int max_cpus)
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{
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/*
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* Be paranoid. Enable the IPI only if we're really about to go SMP.
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*/
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if (cpus_weight(cpu_possible_map))
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set_c0_status(STATUSF_IP5);
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}
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/*
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* Firmware CPU startup hook
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* Complicated by PMON's weird interface which tries to minimic the UNIX fork.
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* It launches the next * available CPU and copies some information on the
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* stack so the first thing we do is throw away that stuff and load useful
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* values into the registers ...
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*/
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void prom_boot_secondary(int cpu, struct task_struct *idle)
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{
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unsigned long gp = (unsigned long) task_thread_info(idle);
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unsigned long sp = __KSTK_TOS(idle);
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secondary_sp = sp;
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secondary_gp = gp;
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spin_unlock(&launch_lock);
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}
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/* Hook for after all CPUs are online */
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void prom_cpus_done(void)
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{
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}
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/*
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* After we've done initial boot, this function is called to allow the
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* board code to clean up state, if needed
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*/
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void prom_init_secondary(void)
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{
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mips_hpt_init(mips_hpt_read());
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set_c0_status(ST0_CO | ST0_IE | ST0_IM);
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}
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void prom_smp_finish(void)
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{
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}
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asmlinkage void titan_mailbox_irq(struct pt_regs *regs)
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{
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int cpu = smp_processor_id();
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unsigned long status;
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if (cpu == 0) {
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status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
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OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
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}
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if (cpu == 1) {
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status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
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OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
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}
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if (status & 0x2)
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smp_call_function_interrupt();
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}
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/*
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* Send inter-processor interrupt
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*/
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void core_send_ipi(int cpu, unsigned int action)
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{
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/*
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* Generate an INTMSG so that it can be sent over to the
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* destination CPU. The INTMSG will put the STATUS bits
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* based on the action desired. An alternative strategy
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* is to write to the Interrupt Set register, read the
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* Interrupt Status register and clear the Interrupt
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* Clear register. The latter is preffered.
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*/
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switch (action) {
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case SMP_RESCHEDULE_YOURSELF:
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if (cpu == 1)
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OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
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else
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OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
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break;
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case SMP_CALL_FUNCTION:
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if (cpu == 1)
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OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
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else
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OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
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break;
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}
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}
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