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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e4823a7a1b
Since the GIC CPU interface is always virtualized by the hardware, we don't have CPU interface state information readily available in our emulation if userland wants to save or restore it. Fortunately the GIC hypervisor interface provides the VMCR register to access the required virtual CPU interface bits. Provide wrappers for GICv2 and GICv3 hosts to have access to this register. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
106 lines
3.2 KiB
C
106 lines
3.2 KiB
C
/*
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* Copyright (C) 2015, 2016 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __KVM_ARM_VGIC_NEW_H__
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#define __KVM_ARM_VGIC_NEW_H__
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#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
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#define IMPLEMENTER_ARM 0x43b
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#define VGIC_ADDR_UNDEF (-1)
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#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
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#define INTERRUPT_ID_BITS_SPIS 10
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#define VGIC_PRI_BITS 5
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#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
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struct vgic_vmcr {
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u32 ctlr;
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u32 abpr;
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u32 bpr;
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u32 pmr;
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};
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struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
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u32 intid);
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bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
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void vgic_kick_vcpus(struct kvm *kvm);
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void vgic_v2_process_maintenance(struct kvm_vcpu *vcpu);
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void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
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void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
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void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
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void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
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int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
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int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
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int offset, u32 *val);
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void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
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enum vgic_type);
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#ifdef CONFIG_KVM_ARM_VGIC_V3
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void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu);
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void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
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void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
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void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
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void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
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void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
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int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t dist_base_address);
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#else
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static inline void vgic_v3_process_maintenance(struct kvm_vcpu *vcpu)
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{
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}
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static inline void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu)
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{
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}
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static inline void vgic_v3_populate_lr(struct kvm_vcpu *vcpu,
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struct vgic_irq *irq, int lr)
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{
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}
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static inline void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr)
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{
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}
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static inline void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
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{
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}
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static inline
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void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
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{
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}
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static inline
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void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
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{
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}
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static inline int vgic_register_redist_iodevs(struct kvm *kvm,
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gpa_t dist_base_address)
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{
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return -ENODEV;
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}
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#endif
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void kvm_register_vgic_device(unsigned long type);
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#endif
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