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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5ea5306c32
One important rule of thumb when desiging a secure software system is that memory should never be writable and executable at the same time. We mostly adhere to this rule in the kernel, except at boot time, when regions may be mapped RWX until after we are done applying alternatives or making other one-off changes. For the alternative patching, we can improve the situation by applying the fixups via the linear mapping, which is never mapped with executable permissions. So map the linear alias of .text with RW- permissions initially, and remove the write permissions as soon as alternative patching has completed. Reviewed-by: Laura Abbott <labbott@redhat.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
182 lines
4.7 KiB
C
182 lines
4.7 KiB
C
/*
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* alternative runtime patching
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* inspired by the x86 version
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*
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* Copyright (C) 2014 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define pr_fmt(fmt) "alternatives: " fmt
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <asm/cacheflush.h>
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#include <asm/alternative.h>
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#include <asm/cpufeature.h>
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#include <asm/insn.h>
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#include <asm/sections.h>
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#include <linux/stop_machine.h>
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#define __ALT_PTR(a,f) (u32 *)((void *)&(a)->f + (a)->f)
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#define ALT_ORIG_PTR(a) __ALT_PTR(a, orig_offset)
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#define ALT_REPL_PTR(a) __ALT_PTR(a, alt_offset)
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struct alt_region {
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struct alt_instr *begin;
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struct alt_instr *end;
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};
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/*
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* Check if the target PC is within an alternative block.
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*/
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static bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc)
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{
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unsigned long replptr;
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if (kernel_text_address(pc))
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return 1;
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replptr = (unsigned long)ALT_REPL_PTR(alt);
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if (pc >= replptr && pc <= (replptr + alt->alt_len))
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return 0;
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/*
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* Branching into *another* alternate sequence is doomed, and
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* we're not even trying to fix it up.
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*/
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BUG();
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}
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#define align_down(x, a) ((unsigned long)(x) & ~(((unsigned long)(a)) - 1))
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static u32 get_alt_insn(struct alt_instr *alt, u32 *insnptr, u32 *altinsnptr)
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{
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u32 insn;
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insn = le32_to_cpu(*altinsnptr);
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if (aarch64_insn_is_branch_imm(insn)) {
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s32 offset = aarch64_get_branch_offset(insn);
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unsigned long target;
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target = (unsigned long)altinsnptr + offset;
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/*
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* If we're branching inside the alternate sequence,
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* do not rewrite the instruction, as it is already
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* correct. Otherwise, generate the new instruction.
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*/
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if (branch_insn_requires_update(alt, target)) {
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offset = target - (unsigned long)insnptr;
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insn = aarch64_set_branch_offset(insn, offset);
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}
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} else if (aarch64_insn_is_adrp(insn)) {
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s32 orig_offset, new_offset;
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unsigned long target;
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/*
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* If we're replacing an adrp instruction, which uses PC-relative
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* immediate addressing, adjust the offset to reflect the new
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* PC. adrp operates on 4K aligned addresses.
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*/
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orig_offset = aarch64_insn_adrp_get_offset(insn);
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target = align_down(altinsnptr, SZ_4K) + orig_offset;
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new_offset = target - align_down(insnptr, SZ_4K);
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insn = aarch64_insn_adrp_set_offset(insn, new_offset);
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} else if (aarch64_insn_uses_literal(insn)) {
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/*
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* Disallow patching unhandled instructions using PC relative
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* literal addresses
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*/
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BUG();
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}
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return insn;
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}
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static void __apply_alternatives(void *alt_region, bool use_linear_alias)
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{
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struct alt_instr *alt;
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struct alt_region *region = alt_region;
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u32 *origptr, *replptr, *updptr;
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for (alt = region->begin; alt < region->end; alt++) {
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u32 insn;
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int i, nr_inst;
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if (!cpus_have_cap(alt->cpufeature))
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continue;
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BUG_ON(alt->alt_len != alt->orig_len);
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pr_info_once("patching kernel code\n");
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origptr = ALT_ORIG_PTR(alt);
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replptr = ALT_REPL_PTR(alt);
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updptr = use_linear_alias ? (u32 *)lm_alias(origptr) : origptr;
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nr_inst = alt->alt_len / sizeof(insn);
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for (i = 0; i < nr_inst; i++) {
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insn = get_alt_insn(alt, origptr + i, replptr + i);
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updptr[i] = cpu_to_le32(insn);
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}
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flush_icache_range((uintptr_t)origptr,
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(uintptr_t)(origptr + nr_inst));
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}
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}
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/*
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* We might be patching the stop_machine state machine, so implement a
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* really simple polling protocol here.
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*/
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static int __apply_alternatives_multi_stop(void *unused)
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{
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static int patched = 0;
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struct alt_region region = {
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.begin = (struct alt_instr *)__alt_instructions,
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.end = (struct alt_instr *)__alt_instructions_end,
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};
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/* We always have a CPU 0 at this point (__init) */
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if (smp_processor_id()) {
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while (!READ_ONCE(patched))
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cpu_relax();
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isb();
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} else {
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BUG_ON(patched);
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__apply_alternatives(®ion, true);
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/* Barriers provided by the cache flushing */
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WRITE_ONCE(patched, 1);
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}
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return 0;
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}
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void __init apply_alternatives_all(void)
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{
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/* better not try code patching on a live SMP system */
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stop_machine(__apply_alternatives_multi_stop, NULL, cpu_online_mask);
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}
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void apply_alternatives(void *start, size_t length)
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{
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struct alt_region region = {
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.begin = start,
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.end = start + length,
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};
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__apply_alternatives(®ion, false);
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}
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