mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 11:26:44 +07:00
a8f447bda3
Rcv and process ansync link status notifications from BE instead of polling for link status in the be_worker thread. Signed-off-by: Sathya Perla <sathyap@serverengines.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1064 lines
28 KiB
C
1064 lines
28 KiB
C
/*
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* Copyright (C) 2005 - 2009 ServerEngines
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation. The full GNU General
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* Public License is included in this distribution in the file called COPYING.
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*
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* Contact Information:
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* linux-drivers@serverengines.com
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*
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* ServerEngines
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* 209 N. Fair Oaks Ave
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* Sunnyvale, CA 94085
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*/
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#include "be.h"
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static void be_mcc_notify(struct be_ctrl_info *ctrl)
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{
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struct be_queue_info *mccq = &ctrl->mcc_obj.q;
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u32 val = 0;
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val |= mccq->id & DB_MCCQ_RING_ID_MASK;
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val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
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iowrite32(val, ctrl->db + DB_MCCQ_OFFSET);
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}
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/* To check if valid bit is set, check the entire word as we don't know
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* the endianness of the data (old entry is host endian while a new entry is
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* little endian) */
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static inline bool be_mcc_compl_is_new(struct be_mcc_cq_entry *compl)
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{
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if (compl->flags != 0) {
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compl->flags = le32_to_cpu(compl->flags);
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BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
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return true;
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} else {
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return false;
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}
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}
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/* Need to reset the entire word that houses the valid bit */
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static inline void be_mcc_compl_use(struct be_mcc_cq_entry *compl)
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{
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compl->flags = 0;
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}
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static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
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struct be_mcc_cq_entry *compl)
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{
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u16 compl_status, extd_status;
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/* Just swap the status to host endian; mcc tag is opaquely copied
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* from mcc_wrb */
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be_dws_le_to_cpu(compl, 4);
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compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
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CQE_STATUS_COMPL_MASK;
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if (compl_status != MCC_STATUS_SUCCESS) {
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extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
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CQE_STATUS_EXTD_MASK;
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printk(KERN_WARNING DRV_NAME
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" error in cmd completion: status(compl/extd)=%d/%d\n",
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compl_status, extd_status);
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return -1;
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}
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return 0;
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}
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/* Link state evt is a string of bytes; no need for endian swapping */
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static void be_async_link_state_process(struct be_ctrl_info *ctrl,
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struct be_async_event_link_state *evt)
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{
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ctrl->async_cb(ctrl->adapter_ctxt,
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evt->port_link_status == ASYNC_EVENT_LINK_UP ? true : false);
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}
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static inline bool is_link_state_evt(u32 trailer)
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{
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return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
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ASYNC_TRAILER_EVENT_CODE_MASK) ==
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ASYNC_EVENT_CODE_LINK_STATE);
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}
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static struct be_mcc_cq_entry *be_mcc_compl_get(struct be_ctrl_info *ctrl)
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{
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struct be_queue_info *mcc_cq = &ctrl->mcc_obj.cq;
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struct be_mcc_cq_entry *compl = queue_tail_node(mcc_cq);
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if (be_mcc_compl_is_new(compl)) {
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queue_tail_inc(mcc_cq);
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return compl;
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}
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return NULL;
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}
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void be_process_mcc(struct be_ctrl_info *ctrl)
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{
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struct be_mcc_cq_entry *compl;
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int num = 0;
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spin_lock_bh(&ctrl->mcc_cq_lock);
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while ((compl = be_mcc_compl_get(ctrl))) {
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if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
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/* Interpret flags as an async trailer */
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BUG_ON(!is_link_state_evt(compl->flags));
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/* Interpret compl as a async link evt */
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be_async_link_state_process(ctrl,
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(struct be_async_event_link_state *) compl);
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} else {
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be_mcc_compl_process(ctrl, compl);
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atomic_dec(&ctrl->mcc_obj.q.used);
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}
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be_mcc_compl_use(compl);
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num++;
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}
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if (num)
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be_cq_notify(ctrl, ctrl->mcc_obj.cq.id, true, num);
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spin_unlock_bh(&ctrl->mcc_cq_lock);
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}
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/* Wait till no more pending mcc requests are present */
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static void be_mcc_wait_compl(struct be_ctrl_info *ctrl)
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{
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#define mcc_timeout 50000 /* 5s timeout */
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int i;
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for (i = 0; i < mcc_timeout; i++) {
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be_process_mcc(ctrl);
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if (atomic_read(&ctrl->mcc_obj.q.used) == 0)
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break;
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udelay(100);
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}
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if (i == mcc_timeout)
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printk(KERN_WARNING DRV_NAME "mcc poll timed out\n");
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}
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/* Notify MCC requests and wait for completion */
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static void be_mcc_notify_wait(struct be_ctrl_info *ctrl)
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{
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be_mcc_notify(ctrl);
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be_mcc_wait_compl(ctrl);
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}
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static int be_mbox_db_ready_wait(void __iomem *db)
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{
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int cnt = 0, wait = 5;
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u32 ready;
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do {
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ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
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if (ready)
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break;
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if (cnt > 200000) {
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printk(KERN_WARNING DRV_NAME
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": mbox_db poll timed out\n");
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return -1;
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}
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if (cnt > 50)
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wait = 200;
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cnt += wait;
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udelay(wait);
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} while (true);
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return 0;
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}
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/*
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* Insert the mailbox address into the doorbell in two steps
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* Polls on the mbox doorbell till a command completion (or a timeout) occurs
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*/
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static int be_mbox_db_ring(struct be_ctrl_info *ctrl)
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{
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int status;
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u32 val = 0;
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void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
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struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
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struct be_mcc_mailbox *mbox = mbox_mem->va;
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struct be_mcc_cq_entry *cqe = &mbox->cqe;
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memset(cqe, 0, sizeof(*cqe));
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val &= ~MPU_MAILBOX_DB_RDY_MASK;
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val |= MPU_MAILBOX_DB_HI_MASK;
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/* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
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val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
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iowrite32(val, db);
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/* wait for ready to be set */
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status = be_mbox_db_ready_wait(db);
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if (status != 0)
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return status;
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val = 0;
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val &= ~MPU_MAILBOX_DB_RDY_MASK;
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val &= ~MPU_MAILBOX_DB_HI_MASK;
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/* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
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val |= (u32)(mbox_mem->dma >> 4) << 2;
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iowrite32(val, db);
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status = be_mbox_db_ready_wait(db);
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if (status != 0)
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return status;
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/* A cq entry has been made now */
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if (be_mcc_compl_is_new(cqe)) {
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status = be_mcc_compl_process(ctrl, &mbox->cqe);
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be_mcc_compl_use(cqe);
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if (status)
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return status;
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} else {
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printk(KERN_WARNING DRV_NAME "invalid mailbox completion\n");
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return -1;
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}
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return 0;
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}
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static int be_POST_stage_get(struct be_ctrl_info *ctrl, u16 *stage)
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{
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u32 sem = ioread32(ctrl->csr + MPU_EP_SEMAPHORE_OFFSET);
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*stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
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if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
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return -1;
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else
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return 0;
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}
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static int be_POST_stage_poll(struct be_ctrl_info *ctrl, u16 poll_stage)
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{
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u16 stage, cnt, error;
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for (cnt = 0; cnt < 5000; cnt++) {
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error = be_POST_stage_get(ctrl, &stage);
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if (error)
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return -1;
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if (stage == poll_stage)
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break;
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udelay(1000);
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}
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if (stage != poll_stage)
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return -1;
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return 0;
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}
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int be_cmd_POST(struct be_ctrl_info *ctrl)
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{
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u16 stage, error;
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error = be_POST_stage_get(ctrl, &stage);
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if (error)
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goto err;
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if (stage == POST_STAGE_ARMFW_RDY)
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return 0;
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if (stage != POST_STAGE_AWAITING_HOST_RDY)
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goto err;
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/* On awaiting host rdy, reset and again poll on awaiting host rdy */
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iowrite32(POST_STAGE_BE_RESET, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET);
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error = be_POST_stage_poll(ctrl, POST_STAGE_AWAITING_HOST_RDY);
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if (error)
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goto err;
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/* Now kickoff POST and poll on armfw ready */
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iowrite32(POST_STAGE_HOST_RDY, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET);
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error = be_POST_stage_poll(ctrl, POST_STAGE_ARMFW_RDY);
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if (error)
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goto err;
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return 0;
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err:
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printk(KERN_WARNING DRV_NAME ": ERROR, stage=%d\n", stage);
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return -1;
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}
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static inline void *embedded_payload(struct be_mcc_wrb *wrb)
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{
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return wrb->payload.embedded_payload;
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}
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static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
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{
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return &wrb->payload.sgl[0];
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}
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/* Don't touch the hdr after it's prepared */
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static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
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bool embedded, u8 sge_cnt)
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{
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if (embedded)
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wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
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else
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wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
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MCC_WRB_SGE_CNT_SHIFT;
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wrb->payload_length = payload_len;
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be_dws_cpu_to_le(wrb, 20);
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}
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/* Don't touch the hdr after it's prepared */
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static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
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u8 subsystem, u8 opcode, int cmd_len)
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{
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req_hdr->opcode = opcode;
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req_hdr->subsystem = subsystem;
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req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
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}
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static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
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struct be_dma_mem *mem)
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{
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int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
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u64 dma = (u64)mem->dma;
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for (i = 0; i < buf_pages; i++) {
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pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
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pages[i].hi = cpu_to_le32(upper_32_bits(dma));
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dma += PAGE_SIZE_4K;
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}
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}
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/* Converts interrupt delay in microseconds to multiplier value */
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static u32 eq_delay_to_mult(u32 usec_delay)
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{
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#define MAX_INTR_RATE 651042
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const u32 round = 10;
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u32 multiplier;
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if (usec_delay == 0)
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multiplier = 0;
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else {
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u32 interrupt_rate = 1000000 / usec_delay;
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/* Max delay, corresponding to the lowest interrupt rate */
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if (interrupt_rate == 0)
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multiplier = 1023;
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else {
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multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
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multiplier /= interrupt_rate;
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/* Round the multiplier to the closest value.*/
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multiplier = (multiplier + round/2) / round;
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multiplier = min(multiplier, (u32)1023);
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}
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}
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return multiplier;
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}
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static inline struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
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{
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return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
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}
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static inline struct be_mcc_wrb *wrb_from_mcc(struct be_queue_info *mccq)
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{
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struct be_mcc_wrb *wrb = NULL;
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if (atomic_read(&mccq->used) < mccq->len) {
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wrb = queue_head_node(mccq);
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queue_head_inc(mccq);
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atomic_inc(&mccq->used);
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memset(wrb, 0, sizeof(*wrb));
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}
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return wrb;
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}
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int be_cmd_eq_create(struct be_ctrl_info *ctrl,
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struct be_queue_info *eq, int eq_delay)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_cmd_req_eq_create *req = embedded_payload(wrb);
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struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
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struct be_dma_mem *q_mem = &eq->dma_mem;
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int status;
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spin_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
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be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
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OPCODE_COMMON_EQ_CREATE, sizeof(*req));
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req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
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AMAP_SET_BITS(struct amap_eq_context, func, req->context,
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ctrl->pci_func);
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AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
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/* 4byte eqe*/
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AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
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AMAP_SET_BITS(struct amap_eq_context, count, req->context,
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__ilog2_u32(eq->len/256));
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AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
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eq_delay_to_mult(eq_delay));
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be_dws_cpu_to_le(req->context, sizeof(req->context));
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be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
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status = be_mbox_db_ring(ctrl);
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if (!status) {
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eq->id = le16_to_cpu(resp->eq_id);
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eq->created = true;
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}
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spin_unlock(&ctrl->mbox_lock);
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return status;
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}
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int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr,
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u8 type, bool permanent, u32 if_handle)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_cmd_req_mac_query *req = embedded_payload(wrb);
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struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
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int status;
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spin_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
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be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
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OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
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req->type = type;
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if (permanent) {
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req->permanent = 1;
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} else {
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req->if_id = cpu_to_le16((u16)if_handle);
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req->permanent = 0;
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}
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status = be_mbox_db_ring(ctrl);
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if (!status)
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memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
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spin_unlock(&ctrl->mbox_lock);
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return status;
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}
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int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr,
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u32 if_id, u32 *pmac_id)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_cmd_req_pmac_add *req = embedded_payload(wrb);
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int status;
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spin_lock(&ctrl->mbox_lock);
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memset(wrb, 0, sizeof(*wrb));
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be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
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be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
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OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
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req->if_id = cpu_to_le32(if_id);
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memcpy(req->mac_address, mac_addr, ETH_ALEN);
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status = be_mbox_db_ring(ctrl);
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if (!status) {
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struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
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*pmac_id = le32_to_cpu(resp->pmac_id);
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}
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spin_unlock(&ctrl->mbox_lock);
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return status;
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}
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int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id)
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{
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struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
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struct be_cmd_req_pmac_del *req = embedded_payload(wrb);
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int status;
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spin_lock(&ctrl->mbox_lock);
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|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
|
|
|
|
req->if_id = cpu_to_le32(if_id);
|
|
req->pmac_id = cpu_to_le32(pmac_id);
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_cq_create(struct be_ctrl_info *ctrl,
|
|
struct be_queue_info *cq, struct be_queue_info *eq,
|
|
bool sol_evts, bool no_delay, int coalesce_wm)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_cq_create *req = embedded_payload(wrb);
|
|
struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
|
|
struct be_dma_mem *q_mem = &cq->dma_mem;
|
|
void *ctxt = &req->context;
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_CQ_CREATE, sizeof(*req));
|
|
|
|
req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
|
|
|
|
AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
|
|
AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
|
|
AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
|
|
__ilog2_u32(cq->len/256));
|
|
AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
|
|
AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
|
|
AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_cq_context, func, ctxt, ctrl->pci_func);
|
|
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
if (!status) {
|
|
cq->id = le16_to_cpu(resp->cq_id);
|
|
cq->created = true;
|
|
}
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
static u32 be_encoded_q_len(int q_len)
|
|
{
|
|
u32 len_encoded = fls(q_len); /* log2(len) + 1 */
|
|
if (len_encoded == 16)
|
|
len_encoded = 0;
|
|
return len_encoded;
|
|
}
|
|
|
|
int be_cmd_mccq_create(struct be_ctrl_info *ctrl,
|
|
struct be_queue_info *mccq,
|
|
struct be_queue_info *cq)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_mcc_create *req = embedded_payload(wrb);
|
|
struct be_dma_mem *q_mem = &mccq->dma_mem;
|
|
void *ctxt = &req->context;
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_MCC_CREATE, sizeof(*req));
|
|
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
|
|
|
AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, ctrl->pci_func);
|
|
AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
|
|
be_encoded_q_len(mccq->len));
|
|
AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
|
|
|
|
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
if (!status) {
|
|
struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
|
|
mccq->id = le16_to_cpu(resp->id);
|
|
mccq->created = true;
|
|
}
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_txq_create(struct be_ctrl_info *ctrl,
|
|
struct be_queue_info *txq,
|
|
struct be_queue_info *cq)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_eth_tx_create *req = embedded_payload(wrb);
|
|
struct be_dma_mem *q_mem = &txq->dma_mem;
|
|
void *ctxt = &req->context;
|
|
int status;
|
|
u32 len_encoded;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
|
|
sizeof(*req));
|
|
|
|
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
|
req->ulp_num = BE_ULP1_NUM;
|
|
req->type = BE_ETH_TX_RING_TYPE_STANDARD;
|
|
|
|
len_encoded = fls(txq->len); /* log2(len) + 1 */
|
|
if (len_encoded == 16)
|
|
len_encoded = 0;
|
|
AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, len_encoded);
|
|
AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt,
|
|
ctrl->pci_func);
|
|
AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
|
|
AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
|
|
|
|
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
|
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
if (!status) {
|
|
struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
|
|
txq->id = le16_to_cpu(resp->cid);
|
|
txq->created = true;
|
|
}
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_rxq_create(struct be_ctrl_info *ctrl,
|
|
struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
|
|
u16 max_frame_size, u32 if_id, u32 rss)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_eth_rx_create *req = embedded_payload(wrb);
|
|
struct be_dma_mem *q_mem = &rxq->dma_mem;
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
|
|
sizeof(*req));
|
|
|
|
req->cq_id = cpu_to_le16(cq_id);
|
|
req->frag_size = fls(frag_size) - 1;
|
|
req->num_pages = 2;
|
|
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
|
req->interface_id = cpu_to_le32(if_id);
|
|
req->max_frame_size = cpu_to_le16(max_frame_size);
|
|
req->rss_queue = cpu_to_le32(rss);
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
if (!status) {
|
|
struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
|
|
rxq->id = le16_to_cpu(resp->id);
|
|
rxq->created = true;
|
|
}
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
/* Generic destroyer function for all types of queues */
|
|
int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
|
|
int queue_type)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
|
|
u8 subsys = 0, opcode = 0;
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
switch (queue_type) {
|
|
case QTYPE_EQ:
|
|
subsys = CMD_SUBSYSTEM_COMMON;
|
|
opcode = OPCODE_COMMON_EQ_DESTROY;
|
|
break;
|
|
case QTYPE_CQ:
|
|
subsys = CMD_SUBSYSTEM_COMMON;
|
|
opcode = OPCODE_COMMON_CQ_DESTROY;
|
|
break;
|
|
case QTYPE_TXQ:
|
|
subsys = CMD_SUBSYSTEM_ETH;
|
|
opcode = OPCODE_ETH_TX_DESTROY;
|
|
break;
|
|
case QTYPE_RXQ:
|
|
subsys = CMD_SUBSYSTEM_ETH;
|
|
opcode = OPCODE_ETH_RX_DESTROY;
|
|
break;
|
|
case QTYPE_MCCQ:
|
|
subsys = CMD_SUBSYSTEM_COMMON;
|
|
opcode = OPCODE_COMMON_MCC_DESTROY;
|
|
break;
|
|
default:
|
|
printk(KERN_WARNING DRV_NAME ":bad Q type in Q destroy cmd\n");
|
|
status = -1;
|
|
goto err;
|
|
}
|
|
be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
|
|
req->id = cpu_to_le16(q->id);
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
err:
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
/* Create an rx filtering policy configuration on an i/f */
|
|
int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 flags, u8 *mac,
|
|
bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_if_create *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
|
|
|
|
req->capability_flags = cpu_to_le32(flags);
|
|
req->enable_flags = cpu_to_le32(flags);
|
|
if (!pmac_invalid)
|
|
memcpy(req->mac_addr, mac, ETH_ALEN);
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
if (!status) {
|
|
struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
|
|
*if_handle = le32_to_cpu(resp->interface_id);
|
|
if (!pmac_invalid)
|
|
*pmac_id = le32_to_cpu(resp->pmac_id);
|
|
}
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 interface_id)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_if_destroy *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
|
|
|
|
req->interface_id = cpu_to_le32(interface_id);
|
|
status = be_mbox_db_ring(ctrl);
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
|
|
return status;
|
|
}
|
|
|
|
/* Get stats is a non embedded command: the request is not embedded inside
|
|
* WRB but is a separate dma memory block
|
|
*/
|
|
int be_cmd_get_stats(struct be_ctrl_info *ctrl, struct be_dma_mem *nonemb_cmd)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_get_stats *req = nonemb_cmd->va;
|
|
struct be_sge *sge = nonembedded_sgl(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
memset(req, 0, sizeof(*req));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
|
|
OPCODE_ETH_GET_STATISTICS, sizeof(*req));
|
|
sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
|
|
sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
|
|
sge->len = cpu_to_le32(nonemb_cmd->size);
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
if (!status) {
|
|
struct be_cmd_resp_get_stats *resp = nonemb_cmd->va;
|
|
be_dws_le_to_cpu(&resp->hw_stats, sizeof(resp->hw_stats));
|
|
}
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_link_status_query(struct be_ctrl_info *ctrl,
|
|
bool *link_up)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_link_status *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
|
|
*link_up = false;
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
if (!status) {
|
|
struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
|
|
if (resp->mac_speed != PHY_LINK_SPEED_ZERO)
|
|
*link_up = true;
|
|
}
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_get_fw_version *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
if (!status) {
|
|
struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
|
|
strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
|
|
}
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
/* set the EQ delay interval of an EQ to specified value */
|
|
int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_modify_eq_delay *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
|
|
|
|
req->num_eq = cpu_to_le32(1);
|
|
req->delay[0].eq_id = cpu_to_le32(eq_id);
|
|
req->delay[0].phase = 0;
|
|
req->delay[0].delay_multiplier = cpu_to_le32(eqd);
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id, u16 *vtag_array,
|
|
u32 num, bool untagged, bool promiscuous)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_vlan_config *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
|
|
|
|
req->interface_id = if_id;
|
|
req->promiscuous = promiscuous;
|
|
req->untagged = untagged;
|
|
req->num_vlan = num;
|
|
if (!promiscuous) {
|
|
memcpy(req->normal_vlan, vtag_array,
|
|
req->num_vlan * sizeof(vtag_array[0]));
|
|
}
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
/* Use MCC for this command as it may be called in BH context */
|
|
int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl, u8 port_num, bool en)
|
|
{
|
|
struct be_mcc_wrb *wrb;
|
|
struct be_cmd_req_promiscuous_config *req;
|
|
|
|
spin_lock_bh(&ctrl->mcc_lock);
|
|
|
|
wrb = wrb_from_mcc(&ctrl->mcc_obj.q);
|
|
BUG_ON(!wrb);
|
|
|
|
req = embedded_payload(wrb);
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
|
|
OPCODE_ETH_PROMISCUOUS, sizeof(*req));
|
|
|
|
if (port_num)
|
|
req->port1_promiscuous = en;
|
|
else
|
|
req->port0_promiscuous = en;
|
|
|
|
be_mcc_notify_wait(ctrl);
|
|
|
|
spin_unlock_bh(&ctrl->mcc_lock);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Use MCC for this command as it may be called in BH context
|
|
* (mc == NULL) => multicast promiscous
|
|
*/
|
|
int be_cmd_multicast_set(struct be_ctrl_info *ctrl, u32 if_id,
|
|
struct dev_mc_list *mc_list, u32 mc_count)
|
|
{
|
|
#define BE_MAX_MC 32 /* set mcast promisc if > 32 */
|
|
struct be_mcc_wrb *wrb;
|
|
struct be_cmd_req_mcast_mac_config *req;
|
|
|
|
spin_lock_bh(&ctrl->mcc_lock);
|
|
|
|
wrb = wrb_from_mcc(&ctrl->mcc_obj.q);
|
|
BUG_ON(!wrb);
|
|
|
|
req = embedded_payload(wrb);
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
|
|
|
|
req->interface_id = if_id;
|
|
if (mc_list && mc_count <= BE_MAX_MC) {
|
|
int i;
|
|
struct dev_mc_list *mc;
|
|
|
|
req->num_mac = cpu_to_le16(mc_count);
|
|
|
|
for (mc = mc_list, i = 0; mc; mc = mc->next, i++)
|
|
memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN);
|
|
} else {
|
|
req->promiscuous = 1;
|
|
}
|
|
|
|
be_mcc_notify_wait(ctrl);
|
|
|
|
spin_unlock_bh(&ctrl->mcc_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int be_cmd_set_flow_control(struct be_ctrl_info *ctrl, u32 tx_fc, u32 rx_fc)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_set_flow_control *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
|
|
|
|
req->tx_flow_control = cpu_to_le16((u16)tx_fc);
|
|
req->rx_flow_control = cpu_to_le16((u16)rx_fc);
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_get_flow_control(struct be_ctrl_info *ctrl, u32 *tx_fc, u32 *rx_fc)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_get_flow_control *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
if (!status) {
|
|
struct be_cmd_resp_get_flow_control *resp =
|
|
embedded_payload(wrb);
|
|
*tx_fc = le16_to_cpu(resp->tx_flow_control);
|
|
*rx_fc = le16_to_cpu(resp->rx_flow_control);
|
|
}
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|
|
|
|
int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num)
|
|
{
|
|
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
|
struct be_cmd_req_query_fw_cfg *req = embedded_payload(wrb);
|
|
int status;
|
|
|
|
spin_lock(&ctrl->mbox_lock);
|
|
|
|
memset(wrb, 0, sizeof(*wrb));
|
|
|
|
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
|
|
|
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
|
OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
|
|
|
|
status = be_mbox_db_ring(ctrl);
|
|
if (!status) {
|
|
struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
|
|
*port_num = le32_to_cpu(resp->phys_port);
|
|
}
|
|
|
|
spin_unlock(&ctrl->mbox_lock);
|
|
return status;
|
|
}
|