mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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47c61b3955
Add the necessary logic for supporting the emulated VIRT_SPEC_CTRL MSR to x86_virt_spec_ctrl(). If either X86_FEATURE_LS_CFG_SSBD or X86_FEATURE_VIRT_SPEC_CTRL is set then use the new guest_virt_spec_ctrl argument to check whether the state must be modified on the host. The update reuses speculative_store_bypass_update() so the ZEN-specific sibling coordination can be reused. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_SPECCTRL_H_
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#define _ASM_X86_SPECCTRL_H_
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#include <linux/thread_info.h>
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#include <asm/nospec-branch.h>
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/*
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* On VMENTER we must preserve whatever view of the SPEC_CTRL MSR
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* the guest has, while on VMEXIT we restore the host view. This
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* would be easier if SPEC_CTRL were architecturally maskable or
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* shadowable for guests but this is not (currently) the case.
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* Takes the guest view of SPEC_CTRL MSR as a parameter and also
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* the guest's version of VIRT_SPEC_CTRL, if emulated.
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*/
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extern void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool guest);
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/**
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* x86_spec_ctrl_set_guest - Set speculation control registers for the guest
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* @guest_spec_ctrl: The guest content of MSR_SPEC_CTRL
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* @guest_virt_spec_ctrl: The guest controlled bits of MSR_VIRT_SPEC_CTRL
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* (may get translated to MSR_AMD64_LS_CFG bits)
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*
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* Avoids writing to the MSR if the content/bits are the same
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*/
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static inline
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void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
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{
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x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, true);
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}
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/**
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* x86_spec_ctrl_restore_host - Restore host speculation control registers
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* @guest_spec_ctrl: The guest content of MSR_SPEC_CTRL
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* @guest_virt_spec_ctrl: The guest controlled bits of MSR_VIRT_SPEC_CTRL
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* (may get translated to MSR_AMD64_LS_CFG bits)
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*
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* Avoids writing to the MSR if the content/bits are the same
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*/
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static inline
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void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
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{
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x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, false);
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}
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/* AMD specific Speculative Store Bypass MSR data */
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extern u64 x86_amd_ls_cfg_base;
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extern u64 x86_amd_ls_cfg_ssbd_mask;
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static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn)
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{
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BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
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return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
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}
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static inline unsigned long ssbd_spec_ctrl_to_tif(u64 spec_ctrl)
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{
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BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
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return (spec_ctrl & SPEC_CTRL_SSBD) << (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
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}
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static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
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{
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return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;
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}
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#ifdef CONFIG_SMP
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extern void speculative_store_bypass_ht_init(void);
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#else
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static inline void speculative_store_bypass_ht_init(void) { }
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#endif
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extern void speculative_store_bypass_update(unsigned long tif);
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static inline void speculative_store_bypass_update_current(void)
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{
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speculative_store_bypass_update(current_thread_info()->flags);
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}
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#endif
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