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7effc8ba3e
Signed-off-by: Scott Telford <stelford@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
31 lines
1.1 KiB
Plaintext
31 lines
1.1 KiB
Plaintext
Cadence MHDP DisplayPort SD0801 PHY binding
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===========================================
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This binding describes the Cadence SD0801 PHY hardware included with
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the Cadence MHDP DisplayPort controller.
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-------------------------------------------------------------------------------
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Required properties (controller (parent) node):
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- compatible : Should be "cdns,dp-phy"
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- reg : Defines the following sets of registers in the parent
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mhdp device:
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- Offset of the DPTX PHY configuration registers
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- Offset of the SD0801 PHY configuration registers
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- #phy-cells : from the generic PHY bindings, must be 0.
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Optional properties:
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- num_lanes : Number of DisplayPort lanes to use (1, 2 or 4)
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- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
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2430, 2700, 3240, 4320, 5400 or 8100)
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-------------------------------------------------------------------------------
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Example:
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dp_phy: phy@f0fb030a00 {
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compatible = "cdns,dp-phy";
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reg = <0xf0 0xfb030a00 0x0 0x00000040>,
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<0xf0 0xfb500000 0x0 0x00100000>;
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num_lanes = <4>;
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max_bit_rate = <8100>;
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#phy-cells = <0>;
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};
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