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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7f3af60e5a
* 'intx' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/misc-2.6: PCI MSI: always toggle legacy-INTx-enable bit upon MSI entry/exit
951 lines
24 KiB
C
951 lines
24 KiB
C
/*
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* File: msi.c
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* Purpose: PCI Message Signaled Interrupt (MSI)
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*
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* Copyright (C) 2003-2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#include <linux/err.h>
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#include <linux/mm.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/smp_lock.h>
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#include <linux/pci.h>
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#include <linux/proc_fs.h>
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#include <linux/msi.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include "pci.h"
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#include "msi.h"
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static DEFINE_SPINLOCK(msi_lock);
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static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
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static struct kmem_cache* msi_cachep;
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static int pci_msi_enable = 1;
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static int msi_cache_init(void)
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{
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msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc),
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0, SLAB_HWCACHE_ALIGN, NULL, NULL);
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if (!msi_cachep)
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return -ENOMEM;
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return 0;
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}
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static void msi_set_mask_bit(unsigned int irq, int flag)
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{
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struct msi_desc *entry;
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entry = msi_desc[irq];
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BUG_ON(!entry || !entry->dev);
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switch (entry->msi_attrib.type) {
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case PCI_CAP_ID_MSI:
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if (entry->msi_attrib.maskbit) {
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int pos;
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u32 mask_bits;
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pos = (long)entry->mask_base;
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pci_read_config_dword(entry->dev, pos, &mask_bits);
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mask_bits &= ~(1);
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mask_bits |= flag;
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pci_write_config_dword(entry->dev, pos, mask_bits);
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}
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break;
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case PCI_CAP_ID_MSIX:
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{
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int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
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writel(flag, entry->mask_base + offset);
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break;
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}
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default:
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BUG();
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break;
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}
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}
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void read_msi_msg(unsigned int irq, struct msi_msg *msg)
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{
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struct msi_desc *entry = get_irq_data(irq);
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switch(entry->msi_attrib.type) {
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case PCI_CAP_ID_MSI:
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{
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struct pci_dev *dev = entry->dev;
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int pos = entry->msi_attrib.pos;
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u16 data;
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pci_read_config_dword(dev, msi_lower_address_reg(pos),
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&msg->address_lo);
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if (entry->msi_attrib.is_64) {
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pci_read_config_dword(dev, msi_upper_address_reg(pos),
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&msg->address_hi);
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pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
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} else {
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msg->address_hi = 0;
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pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
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}
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msg->data = data;
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break;
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}
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case PCI_CAP_ID_MSIX:
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{
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void __iomem *base;
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base = entry->mask_base +
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entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
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msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
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msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
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break;
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}
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default:
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BUG();
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}
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}
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void write_msi_msg(unsigned int irq, struct msi_msg *msg)
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{
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struct msi_desc *entry = get_irq_data(irq);
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switch (entry->msi_attrib.type) {
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case PCI_CAP_ID_MSI:
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{
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struct pci_dev *dev = entry->dev;
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int pos = entry->msi_attrib.pos;
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pci_write_config_dword(dev, msi_lower_address_reg(pos),
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msg->address_lo);
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if (entry->msi_attrib.is_64) {
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pci_write_config_dword(dev, msi_upper_address_reg(pos),
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msg->address_hi);
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pci_write_config_word(dev, msi_data_reg(pos, 1),
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msg->data);
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} else {
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pci_write_config_word(dev, msi_data_reg(pos, 0),
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msg->data);
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}
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break;
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}
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case PCI_CAP_ID_MSIX:
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{
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void __iomem *base;
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base = entry->mask_base +
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entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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writel(msg->address_lo,
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base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
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writel(msg->address_hi,
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base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
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writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
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break;
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}
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default:
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BUG();
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}
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}
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void mask_msi_irq(unsigned int irq)
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{
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msi_set_mask_bit(irq, 1);
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}
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void unmask_msi_irq(unsigned int irq)
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{
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msi_set_mask_bit(irq, 0);
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}
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static int msi_free_irq(struct pci_dev* dev, int irq);
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static int msi_init(void)
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{
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static int status = -ENOMEM;
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if (!status)
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return status;
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if (pci_msi_quirk) {
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pci_msi_enable = 0;
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printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n");
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status = -EINVAL;
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return status;
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}
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status = msi_cache_init();
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if (status < 0) {
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pci_msi_enable = 0;
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printk(KERN_WARNING "PCI: MSI cache init failed\n");
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return status;
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}
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return status;
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}
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static struct msi_desc* alloc_msi_entry(void)
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{
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struct msi_desc *entry;
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entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL);
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if (!entry)
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return NULL;
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entry->link.tail = entry->link.head = 0; /* single message */
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entry->dev = NULL;
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return entry;
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}
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static void attach_msi_entry(struct msi_desc *entry, int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&msi_lock, flags);
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msi_desc[irq] = entry;
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spin_unlock_irqrestore(&msi_lock, flags);
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}
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static int create_msi_irq(void)
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{
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struct msi_desc *entry;
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int irq;
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entry = alloc_msi_entry();
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if (!entry)
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return -ENOMEM;
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irq = create_irq();
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if (irq < 0) {
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kmem_cache_free(msi_cachep, entry);
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return -EBUSY;
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}
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set_irq_data(irq, entry);
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return irq;
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}
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static void destroy_msi_irq(unsigned int irq)
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{
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struct msi_desc *entry;
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entry = get_irq_data(irq);
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set_irq_chip(irq, NULL);
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set_irq_data(irq, NULL);
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destroy_irq(irq);
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kmem_cache_free(msi_cachep, entry);
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}
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static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
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{
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u16 control;
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pci_read_config_word(dev, msi_control_reg(pos), &control);
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if (type == PCI_CAP_ID_MSI) {
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/* Set enabled bits to single MSI & enable MSI_enable bit */
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msi_enable(control, 1);
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pci_write_config_word(dev, msi_control_reg(pos), control);
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dev->msi_enabled = 1;
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} else {
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msix_enable(control);
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pci_write_config_word(dev, msi_control_reg(pos), control);
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dev->msix_enabled = 1;
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}
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pci_intx(dev, 0); /* disable intx */
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}
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void disable_msi_mode(struct pci_dev *dev, int pos, int type)
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{
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u16 control;
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pci_read_config_word(dev, msi_control_reg(pos), &control);
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if (type == PCI_CAP_ID_MSI) {
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/* Set enabled bits to single MSI & enable MSI_enable bit */
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msi_disable(control);
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pci_write_config_word(dev, msi_control_reg(pos), control);
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dev->msi_enabled = 0;
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} else {
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msix_disable(control);
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pci_write_config_word(dev, msi_control_reg(pos), control);
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dev->msix_enabled = 0;
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}
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pci_intx(dev, 1); /* enable intx */
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}
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static int msi_lookup_irq(struct pci_dev *dev, int type)
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{
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int irq;
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unsigned long flags;
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spin_lock_irqsave(&msi_lock, flags);
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for (irq = 0; irq < NR_IRQS; irq++) {
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if (!msi_desc[irq] || msi_desc[irq]->dev != dev ||
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msi_desc[irq]->msi_attrib.type != type ||
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msi_desc[irq]->msi_attrib.default_irq != dev->irq)
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continue;
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spin_unlock_irqrestore(&msi_lock, flags);
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/* This pre-assigned MSI irq for this device
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already exits. Override dev->irq with this irq */
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dev->irq = irq;
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return 0;
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}
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spin_unlock_irqrestore(&msi_lock, flags);
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return -EACCES;
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}
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void pci_scan_msi_device(struct pci_dev *dev)
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{
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if (!dev)
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return;
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}
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#ifdef CONFIG_PM
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int pci_save_msi_state(struct pci_dev *dev)
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{
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int pos, i = 0;
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u16 control;
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struct pci_cap_saved_state *save_state;
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u32 *cap;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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if (pos <= 0 || dev->no_msi)
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return 0;
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pci_read_config_word(dev, msi_control_reg(pos), &control);
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if (!(control & PCI_MSI_FLAGS_ENABLE))
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return 0;
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save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
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GFP_KERNEL);
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if (!save_state) {
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printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
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return -ENOMEM;
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}
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cap = &save_state->data[0];
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pci_read_config_dword(dev, pos, &cap[i++]);
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control = cap[0] >> 16;
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pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
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if (control & PCI_MSI_FLAGS_64BIT) {
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pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
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pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
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} else
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pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
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if (control & PCI_MSI_FLAGS_MASKBIT)
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pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
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save_state->cap_nr = PCI_CAP_ID_MSI;
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pci_add_saved_cap(dev, save_state);
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return 0;
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}
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void pci_restore_msi_state(struct pci_dev *dev)
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{
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int i = 0, pos;
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u16 control;
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struct pci_cap_saved_state *save_state;
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u32 *cap;
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save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI);
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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if (!save_state || pos <= 0)
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return;
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cap = &save_state->data[0];
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control = cap[i++] >> 16;
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pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]);
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if (control & PCI_MSI_FLAGS_64BIT) {
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pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]);
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pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]);
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} else
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pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]);
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if (control & PCI_MSI_FLAGS_MASKBIT)
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pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]);
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pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
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enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
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pci_remove_saved_cap(save_state);
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kfree(save_state);
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}
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int pci_save_msix_state(struct pci_dev *dev)
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{
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int pos;
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int temp;
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int irq, head, tail = 0;
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u16 control;
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struct pci_cap_saved_state *save_state;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
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if (pos <= 0 || dev->no_msi)
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return 0;
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/* save the capability */
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pci_read_config_word(dev, msi_control_reg(pos), &control);
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if (!(control & PCI_MSIX_FLAGS_ENABLE))
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return 0;
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save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
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GFP_KERNEL);
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if (!save_state) {
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printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
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return -ENOMEM;
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}
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*((u16 *)&save_state->data[0]) = control;
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/* save the table */
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temp = dev->irq;
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if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
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kfree(save_state);
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return -EINVAL;
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}
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irq = head = dev->irq;
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while (head != tail) {
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struct msi_desc *entry;
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entry = msi_desc[irq];
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read_msi_msg(irq, &entry->msg_save);
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tail = msi_desc[irq]->link.tail;
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irq = tail;
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}
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dev->irq = temp;
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save_state->cap_nr = PCI_CAP_ID_MSIX;
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pci_add_saved_cap(dev, save_state);
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return 0;
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}
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void pci_restore_msix_state(struct pci_dev *dev)
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{
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u16 save;
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int pos;
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int irq, head, tail = 0;
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struct msi_desc *entry;
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int temp;
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struct pci_cap_saved_state *save_state;
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save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
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if (!save_state)
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return;
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save = *((u16 *)&save_state->data[0]);
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pci_remove_saved_cap(save_state);
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kfree(save_state);
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pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
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if (pos <= 0)
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return;
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/* route the table */
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temp = dev->irq;
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if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX))
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return;
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irq = head = dev->irq;
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while (head != tail) {
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entry = msi_desc[irq];
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write_msi_msg(irq, &entry->msg_save);
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tail = msi_desc[irq]->link.tail;
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irq = tail;
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}
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dev->irq = temp;
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pci_write_config_word(dev, msi_control_reg(pos), save);
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enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
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}
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#endif
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/**
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* msi_capability_init - configure device's MSI capability structure
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* @dev: pointer to the pci_dev data structure of MSI device function
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*
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* Setup the MSI capability structure of device function with a single
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* MSI irq, regardless of device function is capable of handling
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* multiple messages. A return of zero indicates the successful setup
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* of an entry zero with the new MSI irq or non-zero for otherwise.
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**/
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static int msi_capability_init(struct pci_dev *dev)
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{
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int status;
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struct msi_desc *entry;
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int pos, irq;
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u16 control;
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pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
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pci_read_config_word(dev, msi_control_reg(pos), &control);
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/* MSI Entry Initialization */
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irq = create_msi_irq();
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if (irq < 0)
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return irq;
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entry = get_irq_data(irq);
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entry->link.head = irq;
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entry->link.tail = irq;
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entry->msi_attrib.type = PCI_CAP_ID_MSI;
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entry->msi_attrib.is_64 = is_64bit_address(control);
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entry->msi_attrib.entry_nr = 0;
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entry->msi_attrib.maskbit = is_mask_bit_support(control);
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entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
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entry->msi_attrib.pos = pos;
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if (is_mask_bit_support(control)) {
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entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
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is_64bit_address(control));
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}
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entry->dev = dev;
|
|
if (entry->msi_attrib.maskbit) {
|
|
unsigned int maskbits, temp;
|
|
/* All MSIs are unmasked by default, Mask them all */
|
|
pci_read_config_dword(dev,
|
|
msi_mask_bits_reg(pos, is_64bit_address(control)),
|
|
&maskbits);
|
|
temp = (1 << multi_msi_capable(control));
|
|
temp = ((temp - 1) & ~temp);
|
|
maskbits |= temp;
|
|
pci_write_config_dword(dev,
|
|
msi_mask_bits_reg(pos, is_64bit_address(control)),
|
|
maskbits);
|
|
}
|
|
/* Configure MSI capability structure */
|
|
status = arch_setup_msi_irq(irq, dev);
|
|
if (status < 0) {
|
|
destroy_msi_irq(irq);
|
|
return status;
|
|
}
|
|
|
|
attach_msi_entry(entry, irq);
|
|
/* Set MSI enabled bits */
|
|
enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
|
|
|
|
dev->irq = irq;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* msix_capability_init - configure device's MSI-X capability
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
|
* @entries: pointer to an array of struct msix_entry entries
|
|
* @nvec: number of @entries
|
|
*
|
|
* Setup the MSI-X capability structure of device function with a
|
|
* single MSI-X irq. A return of zero indicates the successful setup of
|
|
* requested MSI-X entries with allocated irqs or non-zero for otherwise.
|
|
**/
|
|
static int msix_capability_init(struct pci_dev *dev,
|
|
struct msix_entry *entries, int nvec)
|
|
{
|
|
struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
|
|
int status;
|
|
int irq, pos, i, j, nr_entries, temp = 0;
|
|
unsigned long phys_addr;
|
|
u32 table_offset;
|
|
u16 control;
|
|
u8 bir;
|
|
void __iomem *base;
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
|
/* Request & Map MSI-X table region */
|
|
pci_read_config_word(dev, msi_control_reg(pos), &control);
|
|
nr_entries = multi_msix_capable(control);
|
|
|
|
pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
|
|
bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
|
|
table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
|
|
phys_addr = pci_resource_start (dev, bir) + table_offset;
|
|
base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
|
|
if (base == NULL)
|
|
return -ENOMEM;
|
|
|
|
/* MSI-X Table Initialization */
|
|
for (i = 0; i < nvec; i++) {
|
|
irq = create_msi_irq();
|
|
if (irq < 0)
|
|
break;
|
|
|
|
entry = get_irq_data(irq);
|
|
j = entries[i].entry;
|
|
entries[i].vector = irq;
|
|
entry->msi_attrib.type = PCI_CAP_ID_MSIX;
|
|
entry->msi_attrib.is_64 = 1;
|
|
entry->msi_attrib.entry_nr = j;
|
|
entry->msi_attrib.maskbit = 1;
|
|
entry->msi_attrib.default_irq = dev->irq;
|
|
entry->msi_attrib.pos = pos;
|
|
entry->dev = dev;
|
|
entry->mask_base = base;
|
|
if (!head) {
|
|
entry->link.head = irq;
|
|
entry->link.tail = irq;
|
|
head = entry;
|
|
} else {
|
|
entry->link.head = temp;
|
|
entry->link.tail = tail->link.tail;
|
|
tail->link.tail = irq;
|
|
head->link.head = irq;
|
|
}
|
|
temp = irq;
|
|
tail = entry;
|
|
/* Configure MSI-X capability structure */
|
|
status = arch_setup_msi_irq(irq, dev);
|
|
if (status < 0) {
|
|
destroy_msi_irq(irq);
|
|
break;
|
|
}
|
|
|
|
attach_msi_entry(entry, irq);
|
|
}
|
|
if (i != nvec) {
|
|
int avail = i - 1;
|
|
i--;
|
|
for (; i >= 0; i--) {
|
|
irq = (entries + i)->vector;
|
|
msi_free_irq(dev, irq);
|
|
(entries + i)->vector = 0;
|
|
}
|
|
/* If we had some success report the number of irqs
|
|
* we succeeded in setting up.
|
|
*/
|
|
if (avail <= 0)
|
|
avail = -EBUSY;
|
|
return avail;
|
|
}
|
|
/* Set MSI-X enabled bits */
|
|
enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pci_msi_supported - check whether MSI may be enabled on device
|
|
* @dev: pointer to the pci_dev data structure of MSI device function
|
|
*
|
|
* Look at global flags, the device itself, and its parent busses
|
|
* to return 0 if MSI are supported for the device.
|
|
**/
|
|
static
|
|
int pci_msi_supported(struct pci_dev * dev)
|
|
{
|
|
struct pci_bus *bus;
|
|
|
|
/* MSI must be globally enabled and supported by the device */
|
|
if (!pci_msi_enable || !dev || dev->no_msi)
|
|
return -EINVAL;
|
|
|
|
/* Any bridge which does NOT route MSI transactions from it's
|
|
* secondary bus to it's primary bus must set NO_MSI flag on
|
|
* the secondary pci_bus.
|
|
* We expect only arch-specific PCI host bus controller driver
|
|
* or quirks for specific PCI bridges to be setting NO_MSI.
|
|
*/
|
|
for (bus = dev->bus; bus; bus = bus->parent)
|
|
if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pci_enable_msi - configure device's MSI capability structure
|
|
* @dev: pointer to the pci_dev data structure of MSI device function
|
|
*
|
|
* Setup the MSI capability structure of device function with
|
|
* a single MSI irq upon its software driver call to request for
|
|
* MSI mode enabled on its hardware device function. A return of zero
|
|
* indicates the successful setup of an entry zero with the new MSI
|
|
* irq or non-zero for otherwise.
|
|
**/
|
|
int pci_enable_msi(struct pci_dev* dev)
|
|
{
|
|
int pos, temp, status;
|
|
|
|
if (pci_msi_supported(dev) < 0)
|
|
return -EINVAL;
|
|
|
|
temp = dev->irq;
|
|
|
|
status = msi_init();
|
|
if (status < 0)
|
|
return status;
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
|
if (!pos)
|
|
return -EINVAL;
|
|
|
|
WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI));
|
|
|
|
/* Check whether driver already requested for MSI-X irqs */
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
|
if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
|
|
printk(KERN_INFO "PCI: %s: Can't enable MSI. "
|
|
"Device already has MSI-X irq assigned\n",
|
|
pci_name(dev));
|
|
dev->irq = temp;
|
|
return -EINVAL;
|
|
}
|
|
status = msi_capability_init(dev);
|
|
return status;
|
|
}
|
|
|
|
void pci_disable_msi(struct pci_dev* dev)
|
|
{
|
|
struct msi_desc *entry;
|
|
int pos, default_irq;
|
|
u16 control;
|
|
unsigned long flags;
|
|
|
|
if (!pci_msi_enable)
|
|
return;
|
|
if (!dev)
|
|
return;
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
|
if (!pos)
|
|
return;
|
|
|
|
pci_read_config_word(dev, msi_control_reg(pos), &control);
|
|
if (!(control & PCI_MSI_FLAGS_ENABLE))
|
|
return;
|
|
|
|
disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
|
|
|
|
spin_lock_irqsave(&msi_lock, flags);
|
|
entry = msi_desc[dev->irq];
|
|
if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
|
|
spin_unlock_irqrestore(&msi_lock, flags);
|
|
return;
|
|
}
|
|
if (irq_has_action(dev->irq)) {
|
|
spin_unlock_irqrestore(&msi_lock, flags);
|
|
printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
|
|
"free_irq() on MSI irq %d\n",
|
|
pci_name(dev), dev->irq);
|
|
BUG_ON(irq_has_action(dev->irq));
|
|
} else {
|
|
default_irq = entry->msi_attrib.default_irq;
|
|
spin_unlock_irqrestore(&msi_lock, flags);
|
|
msi_free_irq(dev, dev->irq);
|
|
|
|
/* Restore dev->irq to its default pin-assertion irq */
|
|
dev->irq = default_irq;
|
|
}
|
|
}
|
|
|
|
static int msi_free_irq(struct pci_dev* dev, int irq)
|
|
{
|
|
struct msi_desc *entry;
|
|
int head, entry_nr, type;
|
|
void __iomem *base;
|
|
unsigned long flags;
|
|
|
|
arch_teardown_msi_irq(irq);
|
|
|
|
spin_lock_irqsave(&msi_lock, flags);
|
|
entry = msi_desc[irq];
|
|
if (!entry || entry->dev != dev) {
|
|
spin_unlock_irqrestore(&msi_lock, flags);
|
|
return -EINVAL;
|
|
}
|
|
type = entry->msi_attrib.type;
|
|
entry_nr = entry->msi_attrib.entry_nr;
|
|
head = entry->link.head;
|
|
base = entry->mask_base;
|
|
msi_desc[entry->link.head]->link.tail = entry->link.tail;
|
|
msi_desc[entry->link.tail]->link.head = entry->link.head;
|
|
entry->dev = NULL;
|
|
msi_desc[irq] = NULL;
|
|
spin_unlock_irqrestore(&msi_lock, flags);
|
|
|
|
destroy_msi_irq(irq);
|
|
|
|
if (type == PCI_CAP_ID_MSIX) {
|
|
writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE +
|
|
PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
|
|
|
|
if (head == irq)
|
|
iounmap(base);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pci_enable_msix - configure device's MSI-X capability structure
|
|
* @dev: pointer to the pci_dev data structure of MSI-X device function
|
|
* @entries: pointer to an array of MSI-X entries
|
|
* @nvec: number of MSI-X irqs requested for allocation by device driver
|
|
*
|
|
* Setup the MSI-X capability structure of device function with the number
|
|
* of requested irqs upon its software driver call to request for
|
|
* MSI-X mode enabled on its hardware device function. A return of zero
|
|
* indicates the successful configuration of MSI-X capability structure
|
|
* with new allocated MSI-X irqs. A return of < 0 indicates a failure.
|
|
* Or a return of > 0 indicates that driver request is exceeding the number
|
|
* of irqs available. Driver should use the returned value to re-send
|
|
* its request.
|
|
**/
|
|
int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
|
|
{
|
|
int status, pos, nr_entries;
|
|
int i, j, temp;
|
|
u16 control;
|
|
|
|
if (!entries || pci_msi_supported(dev) < 0)
|
|
return -EINVAL;
|
|
|
|
status = msi_init();
|
|
if (status < 0)
|
|
return status;
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
|
if (!pos)
|
|
return -EINVAL;
|
|
|
|
pci_read_config_word(dev, msi_control_reg(pos), &control);
|
|
nr_entries = multi_msix_capable(control);
|
|
if (nvec > nr_entries)
|
|
return -EINVAL;
|
|
|
|
/* Check for any invalid entries */
|
|
for (i = 0; i < nvec; i++) {
|
|
if (entries[i].entry >= nr_entries)
|
|
return -EINVAL; /* invalid entry */
|
|
for (j = i + 1; j < nvec; j++) {
|
|
if (entries[i].entry == entries[j].entry)
|
|
return -EINVAL; /* duplicate entry */
|
|
}
|
|
}
|
|
temp = dev->irq;
|
|
WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX));
|
|
|
|
/* Check whether driver already requested for MSI irq */
|
|
if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
|
|
!msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
|
|
printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
|
|
"Device already has an MSI irq assigned\n",
|
|
pci_name(dev));
|
|
dev->irq = temp;
|
|
return -EINVAL;
|
|
}
|
|
status = msix_capability_init(dev, entries, nvec);
|
|
return status;
|
|
}
|
|
|
|
void pci_disable_msix(struct pci_dev* dev)
|
|
{
|
|
int pos, temp;
|
|
u16 control;
|
|
|
|
if (!pci_msi_enable)
|
|
return;
|
|
if (!dev)
|
|
return;
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
|
if (!pos)
|
|
return;
|
|
|
|
pci_read_config_word(dev, msi_control_reg(pos), &control);
|
|
if (!(control & PCI_MSIX_FLAGS_ENABLE))
|
|
return;
|
|
|
|
disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
|
|
|
|
temp = dev->irq;
|
|
if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
|
|
int irq, head, tail = 0, warning = 0;
|
|
unsigned long flags;
|
|
|
|
irq = head = dev->irq;
|
|
dev->irq = temp; /* Restore pin IRQ */
|
|
while (head != tail) {
|
|
spin_lock_irqsave(&msi_lock, flags);
|
|
tail = msi_desc[irq]->link.tail;
|
|
spin_unlock_irqrestore(&msi_lock, flags);
|
|
if (irq_has_action(irq))
|
|
warning = 1;
|
|
else if (irq != head) /* Release MSI-X irq */
|
|
msi_free_irq(dev, irq);
|
|
irq = tail;
|
|
}
|
|
msi_free_irq(dev, irq);
|
|
if (warning) {
|
|
printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
|
|
"free_irq() on all MSI-X irqs\n",
|
|
pci_name(dev));
|
|
BUG_ON(warning > 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
|
|
* @dev: pointer to the pci_dev data structure of MSI(X) device function
|
|
*
|
|
* Being called during hotplug remove, from which the device function
|
|
* is hot-removed. All previous assigned MSI/MSI-X irqs, if
|
|
* allocated for this device function, are reclaimed to unused state,
|
|
* which may be used later on.
|
|
**/
|
|
void msi_remove_pci_irq_vectors(struct pci_dev* dev)
|
|
{
|
|
int pos, temp;
|
|
unsigned long flags;
|
|
|
|
if (!pci_msi_enable || !dev)
|
|
return;
|
|
|
|
temp = dev->irq; /* Save IOAPIC IRQ */
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
|
if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
|
|
if (irq_has_action(dev->irq)) {
|
|
printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
|
|
"called without free_irq() on MSI irq %d\n",
|
|
pci_name(dev), dev->irq);
|
|
BUG_ON(irq_has_action(dev->irq));
|
|
} else /* Release MSI irq assigned to this device */
|
|
msi_free_irq(dev, dev->irq);
|
|
dev->irq = temp; /* Restore IOAPIC IRQ */
|
|
}
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
|
if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
|
|
int irq, head, tail = 0, warning = 0;
|
|
void __iomem *base = NULL;
|
|
|
|
irq = head = dev->irq;
|
|
while (head != tail) {
|
|
spin_lock_irqsave(&msi_lock, flags);
|
|
tail = msi_desc[irq]->link.tail;
|
|
base = msi_desc[irq]->mask_base;
|
|
spin_unlock_irqrestore(&msi_lock, flags);
|
|
if (irq_has_action(irq))
|
|
warning = 1;
|
|
else if (irq != head) /* Release MSI-X irq */
|
|
msi_free_irq(dev, irq);
|
|
irq = tail;
|
|
}
|
|
msi_free_irq(dev, irq);
|
|
if (warning) {
|
|
iounmap(base);
|
|
printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
|
|
"called without free_irq() on all MSI-X irqs\n",
|
|
pci_name(dev));
|
|
BUG_ON(warning > 0);
|
|
}
|
|
dev->irq = temp; /* Restore IOAPIC IRQ */
|
|
}
|
|
}
|
|
|
|
void pci_no_msi(void)
|
|
{
|
|
pci_msi_enable = 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_enable_msi);
|
|
EXPORT_SYMBOL(pci_disable_msi);
|
|
EXPORT_SYMBOL(pci_enable_msix);
|
|
EXPORT_SYMBOL(pci_disable_msix);
|