mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 09:20:50 +07:00
ab64920c37
- Armada 370/XP suspend/resume support
- mvebu SoC driver suspend/resume support
- irqchip
- clocksource
- mbus
- clk
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJUe0lIAAoJEP45WPkGe8Zn/IgP/jOO8c7t7dohRbAe3axzIcaC
DLL7d7j0AScZGXLx1/xJrFFY/P3gn3dlLR7HnT0t4K7vcW0kP4orMGo6FcGicSOZ
VzQf88cOkunKf9NTM1Y0LOXVWTHGuACiXAnxook5A6k+l0xQ1t+uewgEKrg/33VK
6WQ6woe2eYFwghkFwL3ybjttOPM5nxPef6v3TZ3LfwSUBsnSm70F1XiO8xZJH+LM
fL83P409LGWgohwSaXYRdPJcNM0U7QMNo6i/If9NNBhIkdKb6llhQ/DvI+aXUvqB
aD9/4t+Q75yki0mXIin6irltjspWsR8OFbaKZOM5IBFp/XrsKvNU+wy++7z9se9z
qfG1QYmKk3ddI0isoksuIJpfbrlbQqFKCGlNkn8HVi4xCYCijNgb5bUrHQ27Aa4U
GGisAOhqs9Ktpz96WeNKjvNQBSJZ3ESd6tlLrwCei8DwEdT0Z73jr1aEnulurpPG
A3kiUhVpRIU+w0cth5Kix2bZj7JGsykzu1x5xORLE+MN8RSgmoveGyY5CBp2MHrl
NxR/u98SD9I/rWT3DwQIKxM5ZqF4AAnyj4SaSWR/f40kWMU+A+eMEfo8VUeO88fl
ygeeHTghSf58gbdgganRfDyY8OaQHeYNNKbWK6c7vxyMX98vwHOtOb5JS3nn0p7q
Fugy/6qf+ZqYHT4nczJO
=uX+e
-----END PGP SIGNATURE-----
Merge tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu into next/soc
Pull "mvebu SoC suspend changes for v3.19" from Jason Cooper:
- Armada 370/XP suspend/resume support
- mvebu SoC driver suspend/resume support
- irqchip
- clocksource
- mbus
- clk
* tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
76 lines
2.0 KiB
ArmAsm
76 lines
2.0 KiB
ArmAsm
/*
|
|
* Copyright (C) 2014 Marvell
|
|
*
|
|
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
* Gregory Clement <gregory.clement@free-electrons.com>
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*/
|
|
|
|
#include <linux/linkage.h>
|
|
#include <asm/assembler.h>
|
|
|
|
|
|
ENTRY(armada_38x_scu_power_up)
|
|
mrc p15, 4, r1, c15, c0 @ get SCU base address
|
|
orr r1, r1, #0x8 @ SCU CPU Power Status Register
|
|
mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
|
|
and r0, r0, #15
|
|
add r1, r1, r0
|
|
mov r0, #0x0
|
|
strb r0, [r1] @ switch SCU power state to Normal mode
|
|
ret lr
|
|
ENDPROC(armada_38x_scu_power_up)
|
|
|
|
/*
|
|
* This is the entry point through which CPUs exiting cpuidle deep
|
|
* idle state are going.
|
|
*/
|
|
ENTRY(armada_370_xp_cpu_resume)
|
|
ARM_BE8(setend be ) @ go BE8 if entered LE
|
|
/*
|
|
* Disable the MMU that might have been enabled in BootROM if
|
|
* this code is used in the resume path of a suspend/resume
|
|
* cycle.
|
|
*/
|
|
mrc p15, 0, r1, c1, c0, 0
|
|
bic r1, #1
|
|
mcr p15, 0, r1, c1, c0, 0
|
|
bl ll_add_cpu_to_smp_group
|
|
bl ll_enable_coherency
|
|
b cpu_resume
|
|
ENDPROC(armada_370_xp_cpu_resume)
|
|
|
|
ENTRY(armada_38x_cpu_resume)
|
|
/* do we need it for Armada 38x*/
|
|
ARM_BE8(setend be ) @ go BE8 if entered LE
|
|
bl v7_invalidate_l1
|
|
bl armada_38x_scu_power_up
|
|
b cpu_resume
|
|
ENDPROC(armada_38x_cpu_resume)
|
|
|
|
.global mvebu_boot_wa_start
|
|
.global mvebu_boot_wa_end
|
|
|
|
/* The following code will be executed from SRAM */
|
|
ENTRY(mvebu_boot_wa_start)
|
|
mvebu_boot_wa_start:
|
|
ARM_BE8(setend be)
|
|
adr r0, 1f
|
|
ldr r0, [r0] @ load the address of the
|
|
@ resume register
|
|
ldr r0, [r0] @ load the value in the
|
|
@ resume register
|
|
ARM_BE8(rev r0, r0) @ the value is stored LE
|
|
mov pc, r0 @ jump to this value
|
|
/*
|
|
* the last word of this piece of code will be filled by the physical
|
|
* address of the boot address register just after being copied in SRAM
|
|
*/
|
|
1:
|
|
.long .
|
|
mvebu_boot_wa_end:
|
|
ENDPROC(mvebu_boot_wa_end)
|