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We need perf_event.h include for 'struct perf_event_mmap_page'. Link: http://lkml.kernel.org/n/tip-bolqkmqajexhccjb0ib0an8w@git.kernel.org Signed-off-by: Jiri Olsa <jolsa@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Michael Petlan <mpetlan@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/20190822111141.25823-2-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
75 lines
2.4 KiB
C
75 lines
2.4 KiB
C
#ifndef _TOOLS_LINUX_RING_BUFFER_H_
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#define _TOOLS_LINUX_RING_BUFFER_H_
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#include <asm/barrier.h>
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#include <linux/perf_event.h>
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/*
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* Contract with kernel for walking the perf ring buffer from
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* user space requires the following barrier pairing (quote
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* from kernel/events/ring_buffer.c):
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*
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* Since the mmap() consumer (userspace) can run on a
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* different CPU:
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*
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* kernel user
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*
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* if (LOAD ->data_tail) { LOAD ->data_head
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* (A) smp_rmb() (C)
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* STORE $data LOAD $data
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* smp_wmb() (B) smp_mb() (D)
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* STORE ->data_head STORE ->data_tail
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* }
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*
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* Where A pairs with D, and B pairs with C.
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*
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* In our case A is a control dependency that separates the
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* load of the ->data_tail and the stores of $data. In case
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* ->data_tail indicates there is no room in the buffer to
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* store $data we do not.
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*
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* D needs to be a full barrier since it separates the data
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* READ from the tail WRITE.
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*
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* For B a WMB is sufficient since it separates two WRITEs,
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* and for C an RMB is sufficient since it separates two READs.
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*
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* Note, instead of B, C, D we could also use smp_store_release()
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* in B and D as well as smp_load_acquire() in C.
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*
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* However, this optimization does not make sense for all kernel
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* supported architectures since for a fair number it would
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* resolve into READ_ONCE() + smp_mb() pair for smp_load_acquire(),
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* and smp_mb() + WRITE_ONCE() pair for smp_store_release().
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*
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* Thus for those smp_wmb() in B and smp_rmb() in C would still
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* be less expensive. For the case of D this has either the same
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* cost or is less expensive, for example, due to TSO x86 can
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* avoid the CPU barrier entirely.
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*/
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static inline u64 ring_buffer_read_head(struct perf_event_mmap_page *base)
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{
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/*
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* Architectures where smp_load_acquire() does not fallback to
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* READ_ONCE() + smp_mb() pair.
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*/
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#if defined(__x86_64__) || defined(__aarch64__) || defined(__powerpc64__) || \
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defined(__ia64__) || defined(__sparc__) && defined(__arch64__)
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return smp_load_acquire(&base->data_head);
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#else
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u64 head = READ_ONCE(base->data_head);
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smp_rmb();
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return head;
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#endif
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}
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static inline void ring_buffer_write_tail(struct perf_event_mmap_page *base,
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u64 tail)
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{
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smp_store_release(&base->data_tail, tail);
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}
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#endif /* _TOOLS_LINUX_RING_BUFFER_H_ */
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