mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 17:05:48 +07:00
e36d0a2ed5
This allows MSR[EE]=0 lockups to be detected on an OPAL (bare metal) system similarly to the hcall NMI IPI on pseries guests, when the platform/firmware supports it. This is an example of CPU10 spinning with interrupts hard disabled: Watchdog CPU:32 detected Hard LOCKUP other CPUS:10 Watchdog CPU:10 Hard LOCKUP CPU: 10 PID: 4410 Comm: bash Not tainted 4.13.0-rc7-00074-ge89ce1f89f62-dirty #34 task: c0000003a82b4400 task.stack: c0000003af55c000 NIP: c0000000000a7b38 LR: c000000000659044 CTR: c0000000000a7b00 REGS: c00000000fd23d80 TRAP: 0100 Not tainted (4.13.0-rc7-00074-ge89ce1f89f62-dirty) MSR: 90000000000c1033 <SF,HV,ME,IR,DR,RI,LE> CR: 28422222 XER: 20000000 CFAR: c0000000000a7b38 SOFTE: 0 GPR00: c000000000659044 c0000003af55fbb0 c000000001072a00 0000000000000078 GPR04: c0000003c81b5c80 c0000003c81cc7e8 9000000000009033 0000000000000000 GPR08: 0000000000000000 c0000000000a7b00 0000000000000001 9000000000001003 GPR12: c0000000000a7b00 c00000000fd83200 0000000010180df8 0000000010189e60 GPR16: 0000000010189ed8 0000000010151270 000000001018bd88 000000001018de78 GPR20: 00000000370a0668 0000000000000001 00000000101645e0 0000000010163c10 GPR24: 00007fffd14d6294 00007fffd14d6290 c000000000fba6f0 0000000000000004 GPR28: c000000000f351d8 0000000000000078 c000000000f4095c 0000000000000000 NIP [c0000000000a7b38] sysrq_handle_xmon+0x38/0x40 LR [c000000000659044] __handle_sysrq+0xe4/0x270 Call Trace: [c0000003af55fbd0] [c000000000659044] __handle_sysrq+0xe4/0x270 [c0000003af55fc70] [c000000000659810] write_sysrq_trigger+0x70/0xa0 [c0000003af55fca0] [c0000000003da650] proc_reg_write+0xb0/0x110 [c0000003af55fcf0] [c0000000003423bc] __vfs_write+0x6c/0x1b0 [c0000003af55fd90] [c000000000344398] vfs_write+0xd8/0x240 [c0000003af55fde0] [c00000000034632c] SyS_write+0x6c/0x110 [c0000003af55fe30] [c00000000000b220] system_call+0x58/0x6c Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Use kernel types for opal_signal_system_reset()] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
376 lines
8.8 KiB
C
376 lines
8.8 KiB
C
/*
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* SMP support for PowerNV machines.
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*
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* Copyright 2011 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/sched/hotplug.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/cpu.h>
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#include <asm/irq.h>
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#include <asm/smp.h>
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#include <asm/paca.h>
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#include <asm/machdep.h>
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#include <asm/cputable.h>
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#include <asm/firmware.h>
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#include <asm/vdso_datapage.h>
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#include <asm/cputhreads.h>
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#include <asm/xics.h>
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#include <asm/xive.h>
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#include <asm/opal.h>
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#include <asm/runlatch.h>
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#include <asm/code-patching.h>
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#include <asm/dbell.h>
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#include <asm/kvm_ppc.h>
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#include <asm/ppc-opcode.h>
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#include <asm/cpuidle.h>
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#include "powernv.h"
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#ifdef DEBUG
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#include <asm/udbg.h>
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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static void pnv_smp_setup_cpu(int cpu)
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{
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/*
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* P9 workaround for CI vector load (see traps.c),
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* enable the corresponding HMI interrupt
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*/
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if (pvr_version_is(PVR_POWER9))
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mtspr(SPRN_HMEER, mfspr(SPRN_HMEER) | PPC_BIT(17));
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if (xive_enabled())
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xive_smp_setup_cpu();
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else if (cpu != boot_cpuid)
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xics_setup_cpu();
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}
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static int pnv_smp_kick_cpu(int nr)
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{
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unsigned int pcpu;
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unsigned long start_here =
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__pa(ppc_function_entry(generic_secondary_smp_init));
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long rc;
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uint8_t status;
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if (nr < 0 || nr >= nr_cpu_ids)
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return -EINVAL;
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pcpu = get_hard_smp_processor_id(nr);
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/*
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* If we already started or OPAL is not supported, we just
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* kick the CPU via the PACA
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*/
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if (paca[nr].cpu_start || !firmware_has_feature(FW_FEATURE_OPAL))
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goto kick;
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/*
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* At this point, the CPU can either be spinning on the way in
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* from kexec or be inside OPAL waiting to be started for the
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* first time. OPAL v3 allows us to query OPAL to know if it
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* has the CPUs, so we do that
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*/
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rc = opal_query_cpu_status(pcpu, &status);
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if (rc != OPAL_SUCCESS) {
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pr_warn("OPAL Error %ld querying CPU %d state\n", rc, nr);
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return -ENODEV;
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}
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/*
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* Already started, just kick it, probably coming from
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* kexec and spinning
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*/
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if (status == OPAL_THREAD_STARTED)
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goto kick;
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/*
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* Available/inactive, let's kick it
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*/
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if (status == OPAL_THREAD_INACTIVE) {
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pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", nr, pcpu);
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rc = opal_start_cpu(pcpu, start_here);
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if (rc != OPAL_SUCCESS) {
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pr_warn("OPAL Error %ld starting CPU %d\n", rc, nr);
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return -ENODEV;
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}
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} else {
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/*
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* An unavailable CPU (or any other unknown status)
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* shouldn't be started. It should also
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* not be in the possible map but currently it can
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* happen
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*/
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pr_devel("OPAL: CPU %d (HW 0x%x) is unavailable"
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" (status %d)...\n", nr, pcpu, status);
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return -ENODEV;
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}
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kick:
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return smp_generic_kick_cpu(nr);
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static int pnv_smp_cpu_disable(void)
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{
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int cpu = smp_processor_id();
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/* This is identical to pSeries... might consolidate by
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* moving migrate_irqs_away to a ppc_md with default to
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* the generic fixup_irqs. --BenH.
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*/
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set_cpu_online(cpu, false);
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vdso_data->processorCount--;
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if (cpu == boot_cpuid)
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boot_cpuid = cpumask_any(cpu_online_mask);
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if (xive_enabled())
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xive_smp_disable_cpu();
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else
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xics_migrate_irqs_away();
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return 0;
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}
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static void pnv_smp_cpu_kill_self(void)
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{
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unsigned int cpu;
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unsigned long srr1, wmask;
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/* Standard hot unplug procedure */
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/*
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* This hard disables local interurpts, ensuring we have no lazy
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* irqs pending.
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*/
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WARN_ON(irqs_disabled());
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hard_irq_disable();
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WARN_ON(lazy_irq_pending());
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idle_task_exit();
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current->active_mm = NULL; /* for sanity */
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cpu = smp_processor_id();
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DBG("CPU%d offline\n", cpu);
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generic_set_cpu_dead(cpu);
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smp_wmb();
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wmask = SRR1_WAKEMASK;
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if (cpu_has_feature(CPU_FTR_ARCH_207S))
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wmask = SRR1_WAKEMASK_P8;
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while (!generic_check_cpu_restart(cpu)) {
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/*
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* Clear IPI flag, since we don't handle IPIs while
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* offline, except for those when changing micro-threading
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* mode, which are handled explicitly below, and those
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* for coming online, which are handled via
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* generic_check_cpu_restart() calls.
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*/
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kvmppc_set_host_ipi(cpu, 0);
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srr1 = pnv_cpu_offline(cpu);
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WARN_ON(lazy_irq_pending());
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/*
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* If the SRR1 value indicates that we woke up due to
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* an external interrupt, then clear the interrupt.
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* We clear the interrupt before checking for the
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* reason, so as to avoid a race where we wake up for
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* some other reason, find nothing and clear the interrupt
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* just as some other cpu is sending us an interrupt.
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* If we returned from power7_nap as a result of
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* having finished executing in a KVM guest, then srr1
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* contains 0.
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*/
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if (((srr1 & wmask) == SRR1_WAKEEE) ||
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((srr1 & wmask) == SRR1_WAKEHVI)) {
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if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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if (xive_enabled())
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xive_flush_interrupt();
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else
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icp_opal_flush_interrupt();
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} else
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icp_native_flush_interrupt();
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} else if ((srr1 & wmask) == SRR1_WAKEHDBELL) {
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unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER);
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asm volatile(PPC_MSGCLR(%0) : : "r" (msg));
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}
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smp_mb();
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if (cpu_core_split_required())
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continue;
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if (srr1 && !generic_check_cpu_restart(cpu))
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DBG("CPU%d Unexpected exit while offline srr1=%lx!\n",
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cpu, srr1);
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}
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DBG("CPU%d coming online...\n", cpu);
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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static int pnv_cpu_bootable(unsigned int nr)
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{
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/*
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* Starting with POWER8, the subcore logic relies on all threads of a
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* core being booted so that they can participate in split mode
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* switches. So on those machines we ignore the smt_enabled_at_boot
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* setting (smt-enabled on the kernel command line).
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_207S))
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return 1;
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return smp_generic_cpu_bootable(nr);
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}
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static int pnv_smp_prepare_cpu(int cpu)
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{
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if (xive_enabled())
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return xive_smp_prepare_cpu(cpu);
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return 0;
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}
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/* Cause IPI as setup by the interrupt controller (xics or xive) */
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static void (*ic_cause_ipi)(int cpu);
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static void pnv_cause_ipi(int cpu)
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{
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if (doorbell_try_core_ipi(cpu))
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return;
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ic_cause_ipi(cpu);
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}
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static void pnv_p9_dd1_cause_ipi(int cpu)
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{
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int this_cpu = get_cpu();
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/*
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* POWER9 DD1 has a global addressed msgsnd, but for now we restrict
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* IPIs to same core, because it requires additional synchronization
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* for inter-core doorbells which we do not implement.
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*/
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if (cpumask_test_cpu(cpu, cpu_sibling_mask(this_cpu)))
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doorbell_global_ipi(cpu);
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else
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ic_cause_ipi(cpu);
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put_cpu();
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}
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static void __init pnv_smp_probe(void)
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{
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if (xive_enabled())
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xive_smp_probe();
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else
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xics_smp_probe();
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if (cpu_has_feature(CPU_FTR_DBELL)) {
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ic_cause_ipi = smp_ops->cause_ipi;
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WARN_ON(!ic_cause_ipi);
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if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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if (cpu_has_feature(CPU_FTR_POWER9_DD1))
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smp_ops->cause_ipi = pnv_p9_dd1_cause_ipi;
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else
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smp_ops->cause_ipi = doorbell_global_ipi;
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} else {
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smp_ops->cause_ipi = pnv_cause_ipi;
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}
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}
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}
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static int pnv_system_reset_exception(struct pt_regs *regs)
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{
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if (smp_handle_nmi_ipi(regs))
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return 1;
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return 0;
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}
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static int pnv_cause_nmi_ipi(int cpu)
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{
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int64_t rc;
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if (cpu >= 0) {
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rc = opal_signal_system_reset(get_hard_smp_processor_id(cpu));
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if (rc != OPAL_SUCCESS)
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return 0;
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return 1;
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} else if (cpu == NMI_IPI_ALL_OTHERS) {
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bool success = true;
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int c;
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/*
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* We do not use broadcasts (yet), because it's not clear
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* exactly what semantics Linux wants or the firmware should
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* provide.
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*/
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for_each_online_cpu(c) {
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if (c == smp_processor_id())
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continue;
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rc = opal_signal_system_reset(
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get_hard_smp_processor_id(c));
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if (rc != OPAL_SUCCESS)
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success = false;
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}
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if (success)
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return 1;
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/*
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* Caller will fall back to doorbells, which may pick
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* up the remainders.
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*/
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}
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return 0;
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}
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static struct smp_ops_t pnv_smp_ops = {
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.message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
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.cause_ipi = NULL, /* Filled at runtime by pnv_smp_probe() */
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.cause_nmi_ipi = NULL,
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.probe = pnv_smp_probe,
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.prepare_cpu = pnv_smp_prepare_cpu,
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.kick_cpu = pnv_smp_kick_cpu,
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.setup_cpu = pnv_smp_setup_cpu,
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.cpu_bootable = pnv_cpu_bootable,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_disable = pnv_smp_cpu_disable,
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.cpu_die = generic_cpu_die,
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#endif /* CONFIG_HOTPLUG_CPU */
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};
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/* This is called very early during platform setup_arch */
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void __init pnv_smp_init(void)
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{
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if (opal_check_token(OPAL_SIGNAL_SYSTEM_RESET)) {
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ppc_md.system_reset_exception = pnv_system_reset_exception;
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pnv_smp_ops.cause_nmi_ipi = pnv_cause_nmi_ipi;
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}
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smp_ops = &pnv_smp_ops;
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#ifdef CONFIG_HOTPLUG_CPU
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ppc_md.cpu_die = pnv_smp_cpu_kill_self;
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#endif
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}
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