Peter Ujfalusi a74c52def9 clk: ti: clk-7xx: Correct ABE DPLL configuration ... ABE DPLL frequency need to be lowered from 361267200 to 180633600 to facilitate the ATL requironments. The dpll_abe_m2x2_ck clock need to be set to double of ABE DPLL rate in order to have correct clocks for audio. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>		2014-07-31 08:36:58 -07:00
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at91
bcm
berlin
hisilicon
keystone
mmp
mvebu
mxs
qcom	clk: qcom: HDMI source sel is 3 not 2	2014-07-02 16:33:18 -07:00
rockchip
samsung	This batch of fixes is for a handful of clock drivers from Allwinner,	2014-07-13 12:21:04 -07:00
shmobile
sirf
socfpga
spear	clk: spear3xx: Set proper clock parent of uart1/2	2014-07-13 07:12:11 -07:00
st
sunxi	clk: sunxi: fix devm_ioremap_resource error detection code	2014-07-01 23:37:34 -07:00
tegra
ti	clk: ti: clk-7xx: Correct ABE DPLL configuration	2014-07-31 08:36:58 -07:00
ux500
versatile	The clock framework changes for 3.16 are pretty typical: mostly clock	2014-06-07 20:27:30 -07:00
x86
zynq
clk-axi-clkgen.c
clk-axm5516.c
clk-bcm2835.c
clk-composite.c
clk-devres.c
clk-divider.c
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-gate.c
clk-highbank.c
clk-ls1x.c
clk-max77686.c
clk-moxart.c
clk-mux.c
clk-nomadik.c
clk-nspire.c
clk-ppc-corenet.c
clk-s2mps11.c	clk: s2mps11: Fix double free corruption during driver unbind	2014-07-01 21:56:49 -07:00
clk-si570.c
clk-si5351.c
clk-si5351.h
clk-twl6040.c
clk-u300.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c	clk: export __clk_round_rate for providers	2014-06-03 10:38:16 -07:00
clk.h
clkdev.c
Kconfig	The clock framework changes for 3.16 are pretty typical: mostly clock	2014-06-07 20:27:30 -07:00
Makefile	The clock framework changes for 3.16 are pretty typical: mostly clock	2014-06-07 20:27:30 -07:00