mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 03:59:01 +07:00
3cece3abeb
The wait timeouts and delays are directly extracted from the NAND timings and ->chip_delay is only used in legacy path, so let's move it to the nand_legacy struct to make it clear. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
204 lines
4.7 KiB
C
204 lines
4.7 KiB
C
/*
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* Oxford Semiconductor OXNAS NAND driver
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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* Heavily based on plat_nand.c :
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* Author: Vitaly Wool <vitalywool@gmail.com>
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* Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
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* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/of.h>
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/* Nand commands */
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#define OXNAS_NAND_CMD_ALE BIT(18)
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#define OXNAS_NAND_CMD_CLE BIT(19)
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#define OXNAS_NAND_MAX_CHIPS 1
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struct oxnas_nand_ctrl {
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struct nand_controller base;
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void __iomem *io_base;
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struct clk *clk;
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struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
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};
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static uint8_t oxnas_nand_read_byte(struct nand_chip *chip)
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{
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struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
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return readb(oxnas->io_base);
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}
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static void oxnas_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)
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{
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struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
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ioread8_rep(oxnas->io_base, buf, len);
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}
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static void oxnas_nand_write_buf(struct nand_chip *chip, const u8 *buf,
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int len)
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{
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struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
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iowrite8_rep(oxnas->io_base, buf, len);
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}
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/* Single CS command control */
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static void oxnas_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
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unsigned int ctrl)
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{
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struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
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if (ctrl & NAND_CLE)
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writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE);
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else if (ctrl & NAND_ALE)
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writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE);
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}
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/*
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* Probe for the NAND device.
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*/
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static int oxnas_nand_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device_node *nand_np;
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struct oxnas_nand_ctrl *oxnas;
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struct nand_chip *chip;
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struct mtd_info *mtd;
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struct resource *res;
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int nchips = 0;
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int count = 0;
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int err = 0;
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/* Allocate memory for the device structure (and zero it) */
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oxnas = devm_kzalloc(&pdev->dev, sizeof(*oxnas),
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GFP_KERNEL);
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if (!oxnas)
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return -ENOMEM;
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nand_controller_init(&oxnas->base);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(oxnas->io_base))
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return PTR_ERR(oxnas->io_base);
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oxnas->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(oxnas->clk))
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oxnas->clk = NULL;
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/* Only a single chip node is supported */
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count = of_get_child_count(np);
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if (count > 1)
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return -EINVAL;
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err = clk_prepare_enable(oxnas->clk);
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if (err)
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return err;
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device_reset_optional(&pdev->dev);
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for_each_child_of_node(np, nand_np) {
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chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
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GFP_KERNEL);
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if (!chip) {
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err = -ENOMEM;
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goto err_clk_unprepare;
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}
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chip->controller = &oxnas->base;
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nand_set_flash_node(chip, nand_np);
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nand_set_controller_data(chip, oxnas);
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mtd = nand_to_mtd(chip);
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mtd->dev.parent = &pdev->dev;
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mtd->priv = chip;
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chip->legacy.cmd_ctrl = oxnas_nand_cmd_ctrl;
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chip->legacy.read_buf = oxnas_nand_read_buf;
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chip->legacy.read_byte = oxnas_nand_read_byte;
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chip->legacy.write_buf = oxnas_nand_write_buf;
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chip->legacy.chip_delay = 30;
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/* Scan to find existence of the device */
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err = nand_scan(chip, 1);
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if (err)
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goto err_clk_unprepare;
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err = mtd_device_register(mtd, NULL, 0);
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if (err) {
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nand_release(chip);
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goto err_clk_unprepare;
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}
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oxnas->chips[nchips] = chip;
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++nchips;
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}
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/* Exit if no chips found */
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if (!nchips) {
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err = -ENODEV;
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goto err_clk_unprepare;
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}
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platform_set_drvdata(pdev, oxnas);
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return 0;
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err_clk_unprepare:
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clk_disable_unprepare(oxnas->clk);
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return err;
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}
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static int oxnas_nand_remove(struct platform_device *pdev)
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{
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struct oxnas_nand_ctrl *oxnas = platform_get_drvdata(pdev);
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if (oxnas->chips[0])
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nand_release(oxnas->chips[0]);
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clk_disable_unprepare(oxnas->clk);
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return 0;
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}
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static const struct of_device_id oxnas_nand_match[] = {
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{ .compatible = "oxsemi,ox820-nand" },
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{},
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};
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MODULE_DEVICE_TABLE(of, oxnas_nand_match);
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static struct platform_driver oxnas_nand_driver = {
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.probe = oxnas_nand_probe,
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.remove = oxnas_nand_remove,
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.driver = {
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.name = "oxnas_nand",
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.of_match_table = oxnas_nand_match,
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},
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};
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module_platform_driver(oxnas_nand_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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MODULE_DESCRIPTION("Oxnas NAND driver");
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MODULE_ALIAS("platform:oxnas_nand");
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