mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e2b9deb2ad
This patch adds variant data and core support for V8 decoder. This patch also adds the register definition file for new firmware version v8 for MFC. Signed-off-by: Kiran AVND <avnd.kiran@samsung.com> Signed-off-by: Pawel Osciak <posciak@chromium.org> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> [k.debski@samsung.com: Change MFC version macro name to MFC_V8_BIT] Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/*
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* Register definition file for Samsung MFC V8.x Interface (FIMV) driver
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _REGS_MFC_V8_H
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#define _REGS_MFC_V8_H
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#include <linux/sizes.h>
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#include "regs-mfc-v7.h"
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/* Additional registers for v8 */
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#define S5P_FIMV_D_MVC_NUM_VIEWS_V8 0xf104
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#define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 0xf144
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#define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 0xf148
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#define S5P_FIMV_D_MV_BUFFER_SIZE_V8 0xf150
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#define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8 0xf138
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#define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8 0xf13c
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#define S5P_FIMV_D_FIRST_PLANE_DPB_V8 0xf160
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#define S5P_FIMV_D_SECOND_PLANE_DPB_V8 0xf260
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#define S5P_FIMV_D_MV_BUFFER_V8 0xf460
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#define S5P_FIMV_D_NUM_MV_V8 0xf134
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#define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8 0xf154
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#define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8 0xf560
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#define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8 0xf564
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#define S5P_FIMV_D_CPB_BUFFER_ADDR_V8 0xf5b0
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#define S5P_FIMV_D_CPB_BUFFER_SIZE_V8 0xf5b4
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#define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8 0xf5bc
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#define S5P_FIMV_D_CPB_BUFFER_OFFSET_V8 0xf5c0
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#define S5P_FIMV_D_SLICE_IF_ENABLE_V8 0xf5c4
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#define S5P_FIMV_D_STREAM_DATA_SIZE_V8 0xf5d0
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/* Display information register */
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#define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8 0xf600
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#define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8 0xf604
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/* Display status */
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#define S5P_FIMV_D_DISPLAY_STATUS_V8 0xf608
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#define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8 0xf60c
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#define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8 0xf610
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#define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8 0xf618
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#define S5P_FIMV_D_DISPLAY_CROP_INFO1_V8 0xf61c
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#define S5P_FIMV_D_DISPLAY_CROP_INFO2_V8 0xf620
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#define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V8 0xf624
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/* Decoded picture information register */
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#define S5P_FIMV_D_DECODED_STATUS_V8 0xf644
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#define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8 0xf648
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#define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8 0xf64c
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#define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR_V8 0xf650
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#define S5P_FIMV_D_DECODED_FRAME_TYPE_V8 0xf654
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#define S5P_FIMV_D_DECODED_NAL_SIZE_V8 0xf664
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/* Returned value register for specific setting */
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#define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8 0xf674
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#define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8 0xf678
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#define S5P_FIMV_D_MVC_VIEW_ID_V8 0xf6d8
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/* SEI related information */
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#define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8 0xf6dc
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/* MFCv8 Context buffer sizes */
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#define MFC_CTX_BUF_SIZE_V8 (30 * SZ_1K) /* 30KB */
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#define MFC_H264_DEC_CTX_BUF_SIZE_V8 (2 * SZ_1M) /* 2MB */
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#define MFC_OTHER_DEC_CTX_BUF_SIZE_V8 (20 * SZ_1K) /* 20KB */
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/* Buffer size defines */
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#define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h) (((w) * 704) + 2176)
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#define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \
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(((w) * 576 + (h) * 128) + 4128)
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/* BUffer alignment defines */
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#define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8 64
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/* MFCv8 variant defines */
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#define MAX_FW_SIZE_V8 (SZ_1M) /* 1MB */
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#define MAX_CPB_SIZE_V8 (3 * SZ_1M) /* 3MB */
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#define MFC_VERSION_V8 0x80
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#define MFC_NUM_PORTS_V8 1
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#endif /*_REGS_MFC_V8_H*/
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