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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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27f4488872
On machines supporting the OPAL firmware version 1, the system is initially booted under pHyp. We then use a special hypercall to verify if OPAL is available and if it is, we then trigger a "takeover" which disables pHyp and loads the OPAL runtime firmware, giving control to the kernel in hypervisor mode. This patch add the necessary code to detect that the OPAL takeover capability is present when running under PowerVM (aka pHyp) and perform said takeover to get hypervisor control of the processor. To perform the takeover, we must first use RTAS (within Open Firmware runtime environment) to start all processors & threads, in order to give control to OPAL on all of them. We then call the takeover hypercall on everybody, OPAL will re-enter the kernel main entry point passing it a flat device-tree. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
141 lines
2.6 KiB
ArmAsm
141 lines
2.6 KiB
ArmAsm
/*
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* PowerNV OPAL takeover assembly code, for use by prom_init.c
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*
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* Copyright 2011 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/ppc_asm.h>
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#include <asm/hvcall.h>
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#include <asm/asm-offsets.h>
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#include <asm/opal.h>
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#define STK_PARAM(i) (48 + ((i)-3)*8)
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#define H_HAL_TAKEOVER 0x5124
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#define H_HAL_TAKEOVER_QUERY_MAGIC -1
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.text
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_GLOBAL(opal_query_takeover)
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mfcr r0
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stw r0,8(r1)
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std r3,STK_PARAM(r3)(r1)
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std r4,STK_PARAM(r4)(r1)
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li r3,H_HAL_TAKEOVER
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li r4,H_HAL_TAKEOVER_QUERY_MAGIC
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HVSC
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ld r10,STK_PARAM(r3)(r1)
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std r4,0(r10)
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ld r10,STK_PARAM(r4)(r1)
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std r5,0(r10)
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lwz r0,8(r1)
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mtcrf 0xff,r0
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blr
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_GLOBAL(opal_do_takeover)
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mfcr r0
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stw r0,8(r1)
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mflr r0
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std r0,16(r1)
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bl __opal_do_takeover
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ld r0,16(r1)
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mtlr r0
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lwz r0,8(r1)
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mtcrf 0xff,r0
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blr
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__opal_do_takeover:
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ld r4,0(r3)
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ld r5,0x8(r3)
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ld r6,0x10(r3)
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ld r7,0x18(r3)
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ld r8,0x20(r3)
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ld r9,0x28(r3)
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ld r10,0x30(r3)
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ld r11,0x38(r3)
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li r3,H_HAL_TAKEOVER
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HVSC
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blr
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.globl opal_secondary_entry
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opal_secondary_entry:
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mr r31,r3
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mfmsr r11
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li r12,(MSR_SF | MSR_ISF)@highest
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sldi r12,r12,48
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or r11,r11,r12
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mtmsrd r11
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isync
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mfspr r4,SPRN_PIR
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std r4,0(r3)
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1: HMT_LOW
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ld r4,8(r3)
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cmpli cr0,r4,0
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beq 1b
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HMT_MEDIUM
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1: addi r3,r31,16
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bl __opal_do_takeover
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b 1b
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_GLOBAL(opal_enter_rtas)
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mflr r0
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std r0,16(r1)
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stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
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/* Because PROM is running in 32b mode, it clobbers the high order half
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* of all registers that it saves. We therefore save those registers
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* PROM might touch to the stack. (r0, r3-r13 are caller saved)
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*/
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SAVE_GPR(2, r1)
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SAVE_GPR(13, r1)
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SAVE_8GPRS(14, r1)
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SAVE_10GPRS(22, r1)
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mfcr r10
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mfmsr r11
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std r10,_CCR(r1)
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std r11,_MSR(r1)
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/* Get the PROM entrypoint */
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mtlr r5
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/* Switch MSR to 32 bits mode
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*/
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li r12,1
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rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
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andc r11,r11,r12
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li r12,1
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rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
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andc r11,r11,r12
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mtmsrd r11
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isync
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/* Enter RTAS here... */
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blrl
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/* Just make sure that r1 top 32 bits didn't get
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* corrupt by OF
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*/
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rldicl r1,r1,0,32
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/* Restore the MSR (back to 64 bits) */
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ld r0,_MSR(r1)
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MTMSRD(r0)
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isync
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/* Restore other registers */
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REST_GPR(2, r1)
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REST_GPR(13, r1)
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REST_8GPRS(14, r1)
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REST_10GPRS(22, r1)
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ld r4,_CCR(r1)
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mtcr r4
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addi r1,r1,PROM_FRAME_SIZE
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ld r0,16(r1)
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mtlr r0
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blr
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