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This patch focuses on clock setting for RK3288 mmc controller. In RK3288 mmc controller, CLKDIV register can only be set 0 or 1, and if DDR 8bit mode, CLKDIV register must be set 1. Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
26 lines
825 B
Plaintext
26 lines
825 B
Plaintext
* Rockchip specific extensions to the Synopsys Designware Mobile
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Storage Host Controller
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The Synopsys designware mobile storage host controller is used to interface
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a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
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differences between the core Synopsys dw mshc controller properties described
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by synopsys-dw-mshc.txt and the properties used by the Rockchip specific
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extensions to the Synopsys Designware Mobile Storage Host Controller.
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Required Properties:
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* compatible: should be
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- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
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before RK3288
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- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
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Example:
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rkdwmmc0@12200000 {
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compatible = "rockchip,rk3288-dw-mshc";
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reg = <0x12200000 0x1000>;
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interrupts = <0 75 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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