Stefan Roese e278fc71b2 mtd: fsmc_nand: Add BCH4 SW ECC support for SPEAr600 ... This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength. To enable SW BCH4, you need to specify this in your nand controller DT node: nand-ecc-mode = "soft_bch"; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; Tested on a custom SPEAr600 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Viresh Kumar <viresh.kumar@linaro.org> [Brian: tweaked the comments a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com>		2015-10-26 13:19:40 -07:00
..
chips
devices	mtd: docg3: off by one in doc_register_sysfs()	2015-10-26 11:45:30 -07:00
lpddr	mtd: lpddr: show parent device in sysfs	2015-10-13 09:21:17 -07:00
maps	mtd: maps: rbtx4939-flash: fix compile error	2015-10-19 18:21:25 -07:00
nand	mtd: fsmc_nand: Add BCH4 SW ECC support for SPEAr600	2015-10-26 13:19:40 -07:00
onenand	mtd: onenand: omap2: drop owner and name assignment	2015-10-13 12:56:43 -07:00
spi-nor	mtd: fsl-quadspi: Include <linux/sizes.h> to avoid build error	2015-10-19 09:50:46 -07:00
tests
ubi
afs.c
ar7part.c
bcm47xxpart.c
bcm63xxpart.c
cmdlinepart.c
ftl.c
inftlcore.c
inftlmount.c
Kconfig
Makefile
mtd_blkdevs.c
mtdblock_ro.c
mtdblock.c
mtdchar.c
mtdconcat.c
mtdcore.c	mtd: core: set some defaults when dev.parent is set	2015-10-13 09:21:13 -07:00
mtdcore.h
mtdoops.c
mtdpart.c
mtdsuper.c
mtdswap.c
nftlcore.c
nftlmount.c
ofpart.c
redboot.c
rfd_ftl.c
sm_ftl.c
sm_ftl.h
ssfdc.c