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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a31f82057c
The patch to call mp_config_acpi_gsi() from the ACPI IRQ registration code never got mainline because there were open discussions about it. This call is needed to properly update the kernel's copy of the mptable, when the update_mptable boot parameter is needed. Now that the dust has settled with the APIC unification, and since there were no objections when the patch was re-submitted, try this again. [ Impact: fix the update_mptable boot parameter ] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Len Brown <lenb@kernel.org> LKML-Reference: <4A01C387.7090103@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
164 lines
4.3 KiB
C
164 lines
4.3 KiB
C
#ifndef _ASM_X86_MPSPEC_H
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#define _ASM_X86_MPSPEC_H
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#include <linux/init.h>
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#include <asm/mpspec_def.h>
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extern int apic_version[MAX_APICS];
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extern int pic_mode;
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#ifdef CONFIG_X86_32
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/*
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* Summit or generic (i.e. installer) kernels need lots of bus entries.
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* Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets.
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*/
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#if CONFIG_BASE_SMALL == 0
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# define MAX_MP_BUSSES 260
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#else
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# define MAX_MP_BUSSES 32
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#endif
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#define MAX_IRQ_SOURCES 256
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extern unsigned int def_to_bigsmp;
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extern u8 apicid_2_node[];
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#ifdef CONFIG_X86_NUMAQ
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extern int mp_bus_id_to_node[MAX_MP_BUSSES];
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extern int mp_bus_id_to_local[MAX_MP_BUSSES];
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extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
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#endif
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#define MAX_APICID 256
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#else /* CONFIG_X86_64: */
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#define MAX_MP_BUSSES 256
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/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
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#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
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#endif /* CONFIG_X86_64 */
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extern void early_find_smp_config(void);
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extern void early_get_smp_config(void);
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#if defined(CONFIG_MCA) || defined(CONFIG_EISA)
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extern int mp_bus_id_to_type[MAX_MP_BUSSES];
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#endif
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extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
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extern unsigned int boot_cpu_physical_apicid;
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extern unsigned int max_physical_apicid;
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extern int smp_found_config;
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extern int mpc_default_type;
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extern unsigned long mp_lapic_addr;
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extern void get_smp_config(void);
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#ifdef CONFIG_X86_MPPARSE
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extern void find_smp_config(void);
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extern void early_reserve_e820_mpc_new(void);
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#else
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static inline void find_smp_config(void) { }
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static inline void early_reserve_e820_mpc_new(void) { }
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#endif
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void __cpuinit generic_processor_info(int apicid, int version);
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#ifdef CONFIG_ACPI
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extern void mp_register_ioapic(int id, u32 address, u32 gsi_base);
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extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
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u32 gsi);
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extern void mp_config_acpi_legacy_irqs(void);
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struct device;
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extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level,
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int active_high_low);
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extern int acpi_probe_gsi(void);
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#ifdef CONFIG_X86_IO_APIC
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extern int mp_find_ioapic(int gsi);
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extern int mp_find_ioapic_pin(int ioapic, int gsi);
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#endif
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#else /* !CONFIG_ACPI: */
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static inline int acpi_probe_gsi(void)
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{
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return 0;
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}
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#endif /* CONFIG_ACPI */
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#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
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struct physid_mask {
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unsigned long mask[PHYSID_ARRAY_SIZE];
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};
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typedef struct physid_mask physid_mask_t;
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#define physid_set(physid, map) set_bit(physid, (map).mask)
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#define physid_clear(physid, map) clear_bit(physid, (map).mask)
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#define physid_isset(physid, map) test_bit(physid, (map).mask)
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#define physid_test_and_set(physid, map) \
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test_and_set_bit(physid, (map).mask)
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#define physids_and(dst, src1, src2) \
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bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
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#define physids_or(dst, src1, src2) \
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bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
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#define physids_clear(map) \
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bitmap_zero((map).mask, MAX_APICS)
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#define physids_complement(dst, src) \
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bitmap_complement((dst).mask, (src).mask, MAX_APICS)
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#define physids_empty(map) \
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bitmap_empty((map).mask, MAX_APICS)
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#define physids_equal(map1, map2) \
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bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
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#define physids_weight(map) \
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bitmap_weight((map).mask, MAX_APICS)
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#define physids_shift_right(d, s, n) \
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bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
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#define physids_shift_left(d, s, n) \
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bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
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#define physids_coerce(map) ((map).mask[0])
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#define physids_promote(physids) \
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({ \
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physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
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__physid_mask.mask[0] = physids; \
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__physid_mask; \
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})
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/* Note: will create very large stack frames if physid_mask_t is big */
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#define physid_mask_of_physid(physid) \
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({ \
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physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
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physid_set(physid, __physid_mask); \
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__physid_mask; \
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})
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static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
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{
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physids_clear(*map);
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physid_set(physid, *map);
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}
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#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
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#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
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extern physid_mask_t phys_cpu_present_map;
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extern int generic_mps_oem_check(struct mpc_table *, char *, char *);
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extern int default_acpi_madt_oem_check(char *, char *);
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#endif /* _ASM_X86_MPSPEC_H */
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