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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5651d6aaf4
Using KSEG0ADDR makes code highly MIPS dependent and not portable.
Thanks to the fix a68f376 ("MIPS: io.h: Define `ioremap_cache'") we can
use ioremap_cache which is generic and supported on MIPS as well now.
KSEG0ADDR was translating 0x1c000000 into 0x9c000000. With ioremap_cache
we use MIPS's __ioremap (and then remap_area_pages). This results in
different address (e.g. 0xc0080000) but it still should be cached as
expected and it was successfully tested with BCM47186B0.
Other than that drivers/bcma/driver_chipcommon_sflash.c nicely setups a
struct resource for access window, but we wren't using it. Use it now
and drop duplicated info.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
78 lines
2.4 KiB
C
78 lines
2.4 KiB
C
#ifndef __BCM47XXSFLASH_H
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#define __BCM47XXSFLASH_H
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#include <linux/mtd/mtd.h>
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/* Used for ST flashes only. */
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#define OPCODE_ST_WREN 0x0006 /* Write Enable */
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#define OPCODE_ST_WRDIS 0x0004 /* Write Disable */
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#define OPCODE_ST_RDSR 0x0105 /* Read Status Register */
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#define OPCODE_ST_WRSR 0x0101 /* Write Status Register */
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#define OPCODE_ST_READ 0x0303 /* Read Data Bytes */
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#define OPCODE_ST_PP 0x0302 /* Page Program */
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#define OPCODE_ST_SE 0x02d8 /* Sector Erase */
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#define OPCODE_ST_BE 0x00c7 /* Bulk Erase */
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#define OPCODE_ST_DP 0x00b9 /* Deep Power-down */
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#define OPCODE_ST_RES 0x03ab /* Read Electronic Signature */
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#define OPCODE_ST_CSA 0x1000 /* Keep chip select asserted */
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#define OPCODE_ST_SSE 0x0220 /* Sub-sector Erase */
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/* Used for Atmel flashes only. */
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#define OPCODE_AT_READ 0x07e8
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#define OPCODE_AT_PAGE_READ 0x07d2
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#define OPCODE_AT_STATUS 0x01d7
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#define OPCODE_AT_BUF1_WRITE 0x0384
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#define OPCODE_AT_BUF2_WRITE 0x0387
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#define OPCODE_AT_BUF1_ERASE_PROGRAM 0x0283
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#define OPCODE_AT_BUF2_ERASE_PROGRAM 0x0286
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#define OPCODE_AT_BUF1_PROGRAM 0x0288
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#define OPCODE_AT_BUF2_PROGRAM 0x0289
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#define OPCODE_AT_PAGE_ERASE 0x0281
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#define OPCODE_AT_BLOCK_ERASE 0x0250
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#define OPCODE_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
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#define OPCODE_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
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#define OPCODE_AT_BUF1_LOAD 0x0253
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#define OPCODE_AT_BUF2_LOAD 0x0255
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#define OPCODE_AT_BUF1_COMPARE 0x0260
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#define OPCODE_AT_BUF2_COMPARE 0x0261
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#define OPCODE_AT_BUF1_REPROGRAM 0x0258
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#define OPCODE_AT_BUF2_REPROGRAM 0x0259
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/* Status register bits for ST flashes */
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#define SR_ST_WIP 0x01 /* Write In Progress */
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#define SR_ST_WEL 0x02 /* Write Enable Latch */
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#define SR_ST_BP_MASK 0x1c /* Block Protect */
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#define SR_ST_BP_SHIFT 2
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#define SR_ST_SRWD 0x80 /* Status Register Write Disable */
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/* Status register bits for Atmel flashes */
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#define SR_AT_READY 0x80
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#define SR_AT_MISMATCH 0x40
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#define SR_AT_ID_MASK 0x38
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#define SR_AT_ID_SHIFT 3
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struct bcma_drv_cc;
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enum bcm47xxsflash_type {
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BCM47XXSFLASH_TYPE_ATMEL,
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BCM47XXSFLASH_TYPE_ST,
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};
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struct bcm47xxsflash {
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struct bcma_drv_cc *bcma_cc;
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int (*cc_read)(struct bcm47xxsflash *b47s, u16 offset);
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void (*cc_write)(struct bcm47xxsflash *b47s, u16 offset, u32 value);
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enum bcm47xxsflash_type type;
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void __iomem *window;
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u32 blocksize;
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u16 numblocks;
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u32 size;
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struct mtd_info mtd;
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};
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#endif /* BCM47XXSFLASH */
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