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5b5c4e40a3
This patch adds the topology module to the driver. The topology is exposed to
userspace through the sysfs.
The calls to add and remove a device to/from topology are done by the radeon
driver.
v3:
The CPU information, that is provided in the topology section of the amdkfd
driver, is extracted from the CRAT table. Unlike the CPU information located
in /sys/devices/system/cpu/cpu*, which is extracted from the SRAT table.
While the CPU information provided by the CRAT and the SRAT tables might be
identical, the node topology might be different. The SRAT table contains the
topology of CPU nodes only. The CRAT table contains the topology of CPU and GPU
nodes together (and can be interleaved). For example CPU node 1 in SRAT can be
CPU node 3 in CRAT. Furthermore it's worth to mention that the CRAT table
contains only HSA compatible nodes (nodes which are compliant with the HSA
spec).
To recap, amdkfd exposes a different kind of topology than the one exposed by
/sys/devices/system/cpu/cpu even though it may contain similar information.
v4:
The topology module doesn't support uevent handling and doesn't notify the
userspace about runtime modifications. It is up to the userspace to acquire
snapshots of the topology information created by the amdkfd and exposed
in sysfs.
The following is an example of how the topology looks on a Kaveri A10-7850K
system with amdkfd installed:
/sys/devices/virtual/kfd/kfd/
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--- topology/
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|--- generation_id
|--- system_properties
|--- nodes/
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|--- 0/
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|--- gpu_id
|--- name
|--- properties
|--- caches/
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|--- 0/
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|--- properties
|--- 1/
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|--- properties
|--- 2/
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|--- properties
|--- io_links/
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|--- mem_banks/
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|--- 0/
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|--- properties
|--- 1/
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|--- properties
|--- 2/
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|--- properties
|--- 3/
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|--- properties
v5:
Move amdkfd from drm/radeon/ to drm/amd/
Add a check if dev->gpu pointer is null before accessing it in the
node_show function in kfd_topology.c
This situation may occur when amdkfd is loaded and there is a GPU with a CRAT
table, but that GPU isn't supported by amdkfd
Signed-off-by: Evgeny Pinchuk <evgeny.pinchuk@amd.com>
Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
295 lines
7.6 KiB
C
295 lines
7.6 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef KFD_CRAT_H_INCLUDED
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#define KFD_CRAT_H_INCLUDED
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#include <linux/types.h>
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#pragma pack(1)
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/*
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* 4CC signature values for the CRAT and CDIT ACPI tables
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*/
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#define CRAT_SIGNATURE "CRAT"
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#define CDIT_SIGNATURE "CDIT"
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/*
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* Component Resource Association Table (CRAT)
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*/
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#define CRAT_OEMID_LENGTH 6
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#define CRAT_OEMTABLEID_LENGTH 8
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#define CRAT_RESERVED_LENGTH 6
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#define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
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struct crat_header {
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uint32_t signature;
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uint32_t length;
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uint8_t revision;
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uint8_t checksum;
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uint8_t oem_id[CRAT_OEMID_LENGTH];
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uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH];
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uint32_t oem_revision;
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uint32_t creator_id;
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uint32_t creator_revision;
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uint32_t total_entries;
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uint16_t num_domains;
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uint8_t reserved[CRAT_RESERVED_LENGTH];
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};
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/*
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* The header structure is immediately followed by total_entries of the
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* data definitions
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*/
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/*
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* The currently defined subtype entries in the CRAT
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*/
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#define CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY 0
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#define CRAT_SUBTYPE_MEMORY_AFFINITY 1
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#define CRAT_SUBTYPE_CACHE_AFFINITY 2
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#define CRAT_SUBTYPE_TLB_AFFINITY 3
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#define CRAT_SUBTYPE_CCOMPUTE_AFFINITY 4
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#define CRAT_SUBTYPE_IOLINK_AFFINITY 5
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#define CRAT_SUBTYPE_MAX 6
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#define CRAT_SIBLINGMAP_SIZE 32
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/*
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* ComputeUnit Affinity structure and definitions
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*/
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#define CRAT_CU_FLAGS_ENABLED 0x00000001
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#define CRAT_CU_FLAGS_HOT_PLUGGABLE 0x00000002
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#define CRAT_CU_FLAGS_CPU_PRESENT 0x00000004
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#define CRAT_CU_FLAGS_GPU_PRESENT 0x00000008
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#define CRAT_CU_FLAGS_IOMMU_PRESENT 0x00000010
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#define CRAT_CU_FLAGS_RESERVED 0xffffffe0
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#define CRAT_COMPUTEUNIT_RESERVED_LENGTH 4
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struct crat_subtype_computeunit {
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uint8_t type;
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uint8_t length;
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uint16_t reserved;
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uint32_t flags;
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uint32_t proximity_domain;
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uint32_t processor_id_low;
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uint16_t num_cpu_cores;
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uint16_t num_simd_cores;
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uint16_t max_waves_simd;
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uint16_t io_count;
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uint16_t hsa_capability;
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uint16_t lds_size_in_kb;
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uint8_t wave_front_size;
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uint8_t num_banks;
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uint16_t micro_engine_id;
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uint8_t num_arrays;
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uint8_t num_cu_per_array;
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uint8_t num_simd_per_cu;
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uint8_t max_slots_scatch_cu;
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uint8_t reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
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};
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/*
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* HSA Memory Affinity structure and definitions
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*/
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#define CRAT_MEM_FLAGS_ENABLED 0x00000001
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#define CRAT_MEM_FLAGS_HOT_PLUGGABLE 0x00000002
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#define CRAT_MEM_FLAGS_NON_VOLATILE 0x00000004
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#define CRAT_MEM_FLAGS_RESERVED 0xfffffff8
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#define CRAT_MEMORY_RESERVED_LENGTH 8
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struct crat_subtype_memory {
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uint8_t type;
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uint8_t length;
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uint16_t reserved;
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uint32_t flags;
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uint32_t promixity_domain;
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uint32_t base_addr_low;
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uint32_t base_addr_high;
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uint32_t length_low;
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uint32_t length_high;
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uint32_t width;
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uint8_t reserved2[CRAT_MEMORY_RESERVED_LENGTH];
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};
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/*
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* HSA Cache Affinity structure and definitions
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*/
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#define CRAT_CACHE_FLAGS_ENABLED 0x00000001
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#define CRAT_CACHE_FLAGS_DATA_CACHE 0x00000002
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#define CRAT_CACHE_FLAGS_INST_CACHE 0x00000004
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#define CRAT_CACHE_FLAGS_CPU_CACHE 0x00000008
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#define CRAT_CACHE_FLAGS_SIMD_CACHE 0x00000010
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#define CRAT_CACHE_FLAGS_RESERVED 0xffffffe0
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#define CRAT_CACHE_RESERVED_LENGTH 8
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struct crat_subtype_cache {
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uint8_t type;
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uint8_t length;
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uint16_t reserved;
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uint32_t flags;
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uint32_t processor_id_low;
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uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
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uint32_t cache_size;
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uint8_t cache_level;
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uint8_t lines_per_tag;
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uint16_t cache_line_size;
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uint8_t associativity;
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uint8_t cache_properties;
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uint16_t cache_latency;
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uint8_t reserved2[CRAT_CACHE_RESERVED_LENGTH];
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};
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/*
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* HSA TLB Affinity structure and definitions
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*/
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#define CRAT_TLB_FLAGS_ENABLED 0x00000001
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#define CRAT_TLB_FLAGS_DATA_TLB 0x00000002
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#define CRAT_TLB_FLAGS_INST_TLB 0x00000004
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#define CRAT_TLB_FLAGS_CPU_TLB 0x00000008
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#define CRAT_TLB_FLAGS_SIMD_TLB 0x00000010
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#define CRAT_TLB_FLAGS_RESERVED 0xffffffe0
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#define CRAT_TLB_RESERVED_LENGTH 4
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struct crat_subtype_tlb {
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uint8_t type;
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uint8_t length;
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uint16_t reserved;
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uint32_t flags;
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uint32_t processor_id_low;
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uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
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uint32_t tlb_level;
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uint8_t data_tlb_associativity_2mb;
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uint8_t data_tlb_size_2mb;
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uint8_t instruction_tlb_associativity_2mb;
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uint8_t instruction_tlb_size_2mb;
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uint8_t data_tlb_associativity_4k;
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uint8_t data_tlb_size_4k;
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uint8_t instruction_tlb_associativity_4k;
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uint8_t instruction_tlb_size_4k;
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uint8_t data_tlb_associativity_1gb;
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uint8_t data_tlb_size_1gb;
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uint8_t instruction_tlb_associativity_1gb;
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uint8_t instruction_tlb_size_1gb;
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uint8_t reserved2[CRAT_TLB_RESERVED_LENGTH];
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};
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/*
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* HSA CCompute/APU Affinity structure and definitions
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*/
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#define CRAT_CCOMPUTE_FLAGS_ENABLED 0x00000001
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#define CRAT_CCOMPUTE_FLAGS_RESERVED 0xfffffffe
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#define CRAT_CCOMPUTE_RESERVED_LENGTH 16
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struct crat_subtype_ccompute {
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uint8_t type;
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uint8_t length;
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uint16_t reserved;
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uint32_t flags;
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uint32_t processor_id_low;
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uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE];
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uint32_t apu_size;
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uint8_t reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
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};
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/*
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* HSA IO Link Affinity structure and definitions
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*/
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#define CRAT_IOLINK_FLAGS_ENABLED 0x00000001
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#define CRAT_IOLINK_FLAGS_COHERENCY 0x00000002
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#define CRAT_IOLINK_FLAGS_RESERVED 0xfffffffc
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/*
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* IO interface types
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*/
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#define CRAT_IOLINK_TYPE_UNDEFINED 0
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#define CRAT_IOLINK_TYPE_HYPERTRANSPORT 1
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#define CRAT_IOLINK_TYPE_PCIEXPRESS 2
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#define CRAT_IOLINK_TYPE_OTHER 3
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#define CRAT_IOLINK_TYPE_MAX 255
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#define CRAT_IOLINK_RESERVED_LENGTH 24
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struct crat_subtype_iolink {
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uint8_t type;
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uint8_t length;
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uint16_t reserved;
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uint32_t flags;
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uint32_t proximity_domain_from;
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uint32_t proximity_domain_to;
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uint8_t io_interface_type;
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uint8_t version_major;
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uint16_t version_minor;
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uint32_t minimum_latency;
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uint32_t maximum_latency;
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uint32_t minimum_bandwidth_mbs;
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uint32_t maximum_bandwidth_mbs;
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uint32_t recommended_transfer_size;
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uint8_t reserved2[CRAT_IOLINK_RESERVED_LENGTH];
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};
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/*
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* HSA generic sub-type header
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*/
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#define CRAT_SUBTYPE_FLAGS_ENABLED 0x00000001
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struct crat_subtype_generic {
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uint8_t type;
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uint8_t length;
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uint16_t reserved;
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uint32_t flags;
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};
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/*
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* Component Locality Distance Information Table (CDIT)
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*/
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#define CDIT_OEMID_LENGTH 6
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#define CDIT_OEMTABLEID_LENGTH 8
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struct cdit_header {
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uint32_t signature;
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uint32_t length;
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uint8_t revision;
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uint8_t checksum;
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uint8_t oem_id[CDIT_OEMID_LENGTH];
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uint8_t oem_table_id[CDIT_OEMTABLEID_LENGTH];
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uint32_t oem_revision;
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uint32_t creator_id;
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uint32_t creator_revision;
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uint32_t total_entries;
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uint16_t num_domains;
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uint8_t entry[1];
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};
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#pragma pack()
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#endif /* KFD_CRAT_H_INCLUDED */
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