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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9865853851
Add QUICC Engine (QE) configuration, header files, and QE management and library code that are used by QE devices drivers. Includes Leo's modifications up to, and including, the platform_device to of_device adaptation: "The series of patches add generic QE infrastructure called qe_lib, and MPC8360EMDS board support. Qe_lib is used by QE device drivers such as ucc_geth driver. This version updates QE interrupt controller to use new irq mapping mechanism, addresses all the comments received with last submission and includes some style fixes. v2: Change to use device tree for BCSR and MURAM; Remove I/O port interrupt handling code as it is not generic enough. v3: Address comments from Kumar; Update definition of several device tree nodes; Copyright style change." In addition, the following changes have been made: o removed typedefs o uint -> u32 conversions o removed following defines: QE_SIZEOF_BD, BD_BUFFER_ARG, BD_BUFFER_CLEAR, BD_BUFFER, BD_STATUS_AND_LENGTH_SET, BD_STATUS_AND_LENGTH, and BD_BUFFER_SET because they hid sizeof/in_be32/out_be32 operations from the reader. o fixed qe_snums_init() serial num assignment to use a const array o made CONFIG_UCC_FAST select UCC_SLOW o reduced NR_QE_IC_INTS from 128 to 64 o remove _IO_BASE, etc. defines (not used) o removed irrelevant comments, added others to resemble removed BD_ defines o realigned struct definitions in headers o various other style fixes including things like pinMask -> pin_mask o fixed a ton of whitespace issues o marked ioregs as __be32/__be16 o removed platform_device code and redundant get_qe_base() o removed redundant comments o added cpu_relax() to qe_reset o uncasted all get_property() assignments o eliminated unneeded casts o eliminated immrbar_phys_to_virt (not used) Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Shlomi Gridish <gridish@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
65 lines
2.4 KiB
C
65 lines
2.4 KiB
C
/*
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* include/asm-powerpc/qe_ic.h
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*
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* Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* Description:
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* QE IC external definitions and structure.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ASM_POWERPC_QE_IC_H
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#define _ASM_POWERPC_QE_IC_H
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#include <linux/irq.h>
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#define NUM_OF_QE_IC_GROUPS 6
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/* Flags when we init the QE IC */
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#define QE_IC_SPREADMODE_GRP_W 0x00000001
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#define QE_IC_SPREADMODE_GRP_X 0x00000002
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#define QE_IC_SPREADMODE_GRP_Y 0x00000004
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#define QE_IC_SPREADMODE_GRP_Z 0x00000008
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#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
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#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
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#define QE_IC_LOW_SIGNAL 0x00000100
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#define QE_IC_HIGH_SIGNAL 0x00000200
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#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
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#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
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#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
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#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
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#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
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#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
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#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
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#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
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#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
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#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
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#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
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#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
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#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
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/* QE interrupt sources groups */
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enum qe_ic_grp_id {
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QE_IC_GRP_W = 0, /* QE interrupt controller group W */
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QE_IC_GRP_X, /* QE interrupt controller group X */
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QE_IC_GRP_Y, /* QE interrupt controller group Y */
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QE_IC_GRP_Z, /* QE interrupt controller group Z */
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QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
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QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
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};
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void qe_ic_init(struct device_node *node, unsigned int flags);
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void qe_ic_set_highest_priority(unsigned int virq, int high);
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int qe_ic_set_priority(unsigned int virq, unsigned int priority);
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int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
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#endif /* _ASM_POWERPC_QE_IC_H */
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