Xiaolei Li e1884ffdda mtd: rawnand: mtk: Correct low level time calculation of r/w cycle ... At present, the flow of calculating AC timing of read/write cycle in SDR mode is that: At first, calculate high hold time which is valid for both read and write cycle using the max value between tREH_min and tWH_min. Secondly, calculate WE# pulse width using tWP_min. Thridly, calculate RE# pulse width using the bigger one between tREA_max and tRP_min. But NAND SPEC shows that Controller should also meet write/read cycle time. That is write cycle time should be more than tWC_min and read cycle should be more than tRC_min. Obviously, we do not achieve that now. This patch corrects the low level time calculation to meet minimum read/write cycle time required. After getting the high hold time, WE# low level time will be promised to meet tWP_min and tWC_min requirement, and RE# low level time will be promised to meet tREA_max, tRP_min and tRC_min requirement. Fixes: edfee3619c ("mtd: nand: mtk: add ->setup_data_interface() hook") Cc: stable@vger.kernel.org # v4.17+ Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>		2019-06-27 20:05:24 +02:00
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onenand	mtd: onenand: Add support for 8Gb datasize onenand	2019-06-27 20:05:23 +02:00
raw	mtd: rawnand: mtk: Correct low level time calculation of r/w cycle	2019-06-27 20:05:24 +02:00
spi	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
bbt.c	mtd: nand: Fix memory allocation in nanddev_bbt_init()	2018-11-28 15:41:50 +01:00
core.c	mtd: nand: Add max_bad_eraseblocks_per_lun info to memorg	2019-04-08 10:21:08 +02:00
Kconfig	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
Makefile	mtd: nand: Add core infrastructure to support SPI NANDs	2018-07-18 09:24:10 +02:00