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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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64b3d0e812
Currently, we never set _PAGE_COHERENT in the PTEs, we just OR it in in the hash code based on some CPU feature bit. We also manipulate _PAGE_NO_CACHE and _PAGE_GUARDED by hand in all sorts of places. This changes the logic so that instead, the PTE now contains _PAGE_COHERENT for all normal RAM pages thay have I = 0 on platforms that need it. The hash code clears it if the feature bit is not set. It also adds some clean accessors to setup various valid combinations of access flags and change various bits of code to use them instead. This should help having the PTE actually containing the bit combinations that we really want. I also removed _PAGE_GUARDED from _PAGE_BASE on 44x and instead set it explicitely from the TLB miss. I will ultimately remove it completely as it appears that it might not be needed after all but in the meantime, having it in the TLB miss makes things a lot easier. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
84 lines
2.5 KiB
C
84 lines
2.5 KiB
C
#ifndef _ASM_POWERPC_PGTABLE_H
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#define _ASM_POWERPC_PGTABLE_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/processor.h> /* For TASK_SIZE */
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#include <asm/mmu.h>
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#include <asm/page.h>
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struct mm_struct;
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#endif /* !__ASSEMBLY__ */
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#if defined(CONFIG_PPC64)
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# include <asm/pgtable-ppc64.h>
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#else
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# include <asm/pgtable-ppc32.h>
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#endif
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#ifndef __ASSEMBLY__
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/*
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* Macro to mark a page protection value as "uncacheable".
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*/
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#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
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_PAGE_WRITETHRU)
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#define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_NO_CACHE | _PAGE_GUARDED))
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#define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_NO_CACHE))
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#define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_COHERENT))
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#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_COHERENT | _PAGE_WRITETHRU))
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot);
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern unsigned long empty_zero_page[];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern pgd_t swapper_pg_dir[];
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extern void paging_init(void);
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/*
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* kern_addr_valid is intended to indicate whether an address is a valid
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* kernel address. Most 32-bit archs define it as always true (like this)
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* but most 64-bit archs actually perform a test. What should we do here?
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*/
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#define kern_addr_valid(addr) (1)
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#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
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remap_pfn_range(vma, vaddr, pfn, size, prot)
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#include <asm-generic/pgtable.h>
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/*
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* This gets called at the end of handling a page fault, when
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* the kernel has put a new PTE into the page table for the process.
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* We use it to ensure coherency between the i-cache and d-cache
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* for the page which has just been mapped in.
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* On machines which use an MMU hash table, we use this to put a
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* corresponding HPTE into the hash table ahead of time, instead of
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* waiting for the inevitable extra hash-table miss exception.
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*/
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extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PGTABLE_H */
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