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e15de77e74
If the chip locks up, we get into a long polling loop, where the softlockup detector kicks in. See https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=151878 for an example. [adaplas] Chip lockup can occur at 3 points (flush, sync, and wait). Consolidate and allow the driver to go to safe mode cleanly. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
115 lines
5.4 KiB
C
115 lines
5.4 KiB
C
/***************************************************************************\
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|* *|
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|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
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|* *|
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|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
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|* international laws. Users and possessors of this source code are *|
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|* hereby granted a nonexclusive, royalty-free copyright license to *|
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|* use this code in individual and commercial software. *|
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|* *|
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|* Any use of this source code must include, in the user documenta- *|
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|* tion and internal comments to the code, notices to the end user *|
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|* as follows: *|
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|* *|
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|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
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|* *|
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|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
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|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
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|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
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|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
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|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
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|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
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|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
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|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
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|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
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|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
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|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
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|* *|
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|* U.S. Government End Users. This source code is a "commercial *|
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|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
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|* consisting of "commercial computer software" and "commercial *|
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|* computer software documentation," as such terms are used in *|
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|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
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|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
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|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
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|* all U.S. Government End Users acquire the source code with only *|
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|* those rights set forth herein. *|
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|* *|
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\***************************************************************************/
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/*
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* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
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* XFree86 'nv' driver, this source code is provided under MIT-style licensing
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* where the source code is provided "as is" without warranty of any kind.
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* The only usage restriction is for the copyright notices to be retained
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* whenever code is used.
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*
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* Antonino Daplas <adaplas@pol.net> 2005-03-11
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*/
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#ifndef __NV_LOCAL_H__
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#define __NV_LOCAL_H__
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/*
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* This file includes any environment or machine specific values to access the
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* HW. Put all affected includes, typdefs, etc. here so the riva_hw.* files
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* can stay generic in nature.
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*/
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/*
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* HW access macros. These assume memory-mapped I/O, and not normal I/O space.
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*/
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#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i)))
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#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
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#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
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#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i)))
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#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
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#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
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/* VGA I/O is now always done through MMIO */
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#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i)))
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#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i)))
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#define NVDmaNext(par, data) \
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NV_WR32(&(par)->dmaBase[(par)->dmaCurrent++], 0, (data))
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#define NVDmaStart(info, par, tag, size) { \
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if((par)->dmaFree <= (size)) \
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NVDmaWait(info, size); \
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NVDmaNext(par, ((size) << 18) | (tag)); \
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(par)->dmaFree -= ((size) + 1); \
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}
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#if defined(__i386__)
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#define _NV_FENCE() outb(0, 0x3D0);
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#else
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#define _NV_FENCE() mb();
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#endif
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#define WRITE_PUT(par, data) { \
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_NV_FENCE() \
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NV_RD08((par)->FbStart, 0); \
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NV_WR32(&(par)->FIFO[0x0010], 0, (data) << 2); \
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mb(); \
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}
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#define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
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#ifdef __LITTLE_ENDIAN
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#include <linux/bitrev.h>
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#define reverse_order(l) \
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do { \
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u8 *a = (u8 *)(l); \
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a[0] = bitrev8(a[0]); \
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a[1] = bitrev8(a[1]); \
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a[2] = bitrev8(a[2]); \
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a[3] = bitrev8(a[3]); \
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} while(0)
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#else
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#define reverse_order(l) do { } while(0)
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#endif /* __LITTLE_ENDIAN */
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#endif /* __NV_LOCAL_H__ */
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