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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1643accdaa
The OCTEON II SOC has USB EHCI and OHCI controllers connected directly to the internal I/O bus. This patch adds the necessary 'glue' logic to allow ehci-hcd and ohci-hcd drivers to work on OCTEON II. The OCTEON normally runs big-endian, and the ehci/ohci internal registers have host endianness, so we need to select USB_EHCI_BIG_ENDIAN_MMIO. The ehci and ohci blocks share a common clocking and PHY infrastructure. Initialization of the host controller and PHY clocks is common between the two and is factored out into the octeon2-common.c file. Setting of USB_ARCH_HAS_OHCI and USB_ARCH_HAS_EHCI is done in arch/mips/Kconfig in a following patch. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-usb@vger.kernel.org To: dbrownell@users.sourceforge.net Patchwork: http://patchwork.linux-mips.org/patch/1675/ Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
186 lines
4.5 KiB
C
186 lines
4.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2010 Cavium Networks
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <asm/atomic.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-uctlx-defs.h>
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static atomic_t octeon2_usb_clock_start_cnt = ATOMIC_INIT(0);
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void octeon2_usb_clocks_start(void)
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{
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u64 div;
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union cvmx_uctlx_if_ena if_ena;
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union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
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union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
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union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
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int i;
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unsigned long io_clk_64_to_ns;
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if (atomic_inc_return(&octeon2_usb_clock_start_cnt) != 1)
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return;
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io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
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/*
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* Step 1: Wait for voltages stable. That surely happened
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* before starting the kernel.
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*
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* Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
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*/
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if_ena.u64 = 0;
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if_ena.s.en = 1;
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cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
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/* Step 3: Configure the reference clock, PHY, and HCLK */
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clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
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/* 3a */
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clk_rst_ctl.s.p_por = 1;
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clk_rst_ctl.s.hrst = 0;
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clk_rst_ctl.s.p_prst = 0;
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clk_rst_ctl.s.h_clkdiv_rst = 0;
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clk_rst_ctl.s.o_clkdiv_rst = 0;
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clk_rst_ctl.s.h_clkdiv_en = 0;
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clk_rst_ctl.s.o_clkdiv_en = 0;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 3b */
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/* 12MHz crystal. */
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clk_rst_ctl.s.p_refclk_sel = 0;
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clk_rst_ctl.s.p_refclk_div = 0;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 3c */
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div = octeon_get_io_clock_rate() / 130000000ull;
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switch (div) {
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case 0:
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div = 1;
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break;
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case 1:
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case 2:
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case 3:
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case 4:
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break;
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case 5:
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div = 4;
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break;
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case 6:
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case 7:
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div = 6;
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break;
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case 8:
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case 9:
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case 10:
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case 11:
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div = 8;
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break;
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default:
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div = 12;
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break;
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}
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clk_rst_ctl.s.h_div = div;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Read it back, */
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clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
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clk_rst_ctl.s.h_clkdiv_en = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 3d */
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clk_rst_ctl.s.h_clkdiv_rst = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 3e: delay 64 io clocks */
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ndelay(io_clk_64_to_ns);
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/*
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* Step 4: Program the power-on reset field in the UCTL
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* clock-reset-control register.
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*/
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clk_rst_ctl.s.p_por = 0;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Step 5: Wait 1 ms for the PHY clock to start. */
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mdelay(1);
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/*
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* Step 6: Program the reset input from automatic test
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* equipment field in the UPHY CSR
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*/
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uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
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uphy_ctl_status.s.ate_reset = 1;
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cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
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/* Step 7: Wait for at least 10ns. */
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ndelay(10);
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/* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
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uphy_ctl_status.s.ate_reset = 0;
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cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
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/*
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* Step 9: Wait for at least 20ns for UPHY to output PHY clock
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* signals and OHCI_CLK48
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*/
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ndelay(20);
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/* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
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/* 10a */
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clk_rst_ctl.s.o_clkdiv_rst = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 10b */
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clk_rst_ctl.s.o_clkdiv_en = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* 10c */
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ndelay(io_clk_64_to_ns);
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/*
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* Step 11: Program the PHY reset field:
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* UCTL0_CLK_RST_CTL[P_PRST] = 1
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*/
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clk_rst_ctl.s.p_prst = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Step 12: Wait 1 uS. */
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udelay(1);
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/* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
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clk_rst_ctl.s.hrst = 1;
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cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
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/* Now we can set some other registers. */
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for (i = 0; i <= 1; i++) {
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port_ctl_status.u64 =
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cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
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/* Set txvreftune to 15 to obtain complient 'eye' diagram. */
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port_ctl_status.s.txvreftune = 15;
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cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
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port_ctl_status.u64);
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}
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}
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EXPORT_SYMBOL(octeon2_usb_clocks_start);
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void octeon2_usb_clocks_stop(void)
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{
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union cvmx_uctlx_if_ena if_ena;
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if (atomic_dec_return(&octeon2_usb_clock_start_cnt) != 0)
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return;
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if_ena.u64 = 0;
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if_ena.s.en = 0;
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cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
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}
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EXPORT_SYMBOL(octeon2_usb_clocks_stop);
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