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186172f465
The Allwinner H6 SoC features a Ethernet MAC that is similar to the one in A64. Add a compatible string for it with A64 fallback compatible string, in this case the A64 driver can be used. The "internal" PHY is not internal from the perspective of the H6 main die, instead it's on the co-packaged AC200 chip, and connected to the main die with RMII at the in-package Port A PIO bank. So from the SoC driver side it needs no special treatment. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
202 lines
5.5 KiB
Plaintext
202 lines
5.5 KiB
Plaintext
* Allwinner sun8i GMAC ethernet controller
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This device is a platform glue layer for stmmac.
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Please see stmmac.txt for the other unchanged properties.
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Required properties:
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- compatible: must be one of the following string:
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"allwinner,sun8i-a83t-emac"
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"allwinner,sun8i-h3-emac"
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"allwinner,sun8i-r40-gmac"
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"allwinner,sun8i-v3s-emac"
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"allwinner,sun50i-a64-emac"
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"allwinner,sun50i-h6-emac", "allwinner-sun50i-a64-emac"
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- reg: address and length of the register for the device.
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- interrupts: interrupt for the device
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- interrupt-names: must be "macirq"
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- clocks: A phandle to the reference clock for this device
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- clock-names: must be "stmmaceth"
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- resets: A phandle to the reset control for this device
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- reset-names: must be "stmmaceth"
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- phy-mode: See ethernet.txt
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- phy-handle: See ethernet.txt
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- syscon: A phandle to the device containing the EMAC or GMAC clock register
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Optional properties:
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- allwinner,tx-delay-ps: TX clock delay chain value in ps.
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Range is 0-700. Default is 0.
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Unavailable for allwinner,sun8i-r40-gmac
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- allwinner,rx-delay-ps: RX clock delay chain value in ps.
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Range is 0-3100. Default is 0.
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Range is 0-700 for allwinner,sun8i-r40-gmac
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Both delay properties need to be a multiple of 100. They control the
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clock delay for external RGMII PHY. They do not apply to the internal
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PHY or external non-RGMII PHYs.
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Optional properties for the following compatibles:
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- "allwinner,sun8i-h3-emac",
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- "allwinner,sun8i-v3s-emac":
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- allwinner,leds-active-low: EPHY LEDs are active low
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Required child node of emac:
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- mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
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Required properties of the mdio node:
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- #address-cells: shall be 1
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- #size-cells: shall be 0
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The device node referenced by "phy" or "phy-handle" must be a child node
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of the mdio node. See phy.txt for the generic PHY bindings.
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The following compatibles require that the emac node have a mdio-mux child
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node called "mdio-mux":
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- "allwinner,sun8i-h3-emac"
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- "allwinner,sun8i-v3s-emac":
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Required properties for the mdio-mux node:
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- compatible = "allwinner,sun8i-h3-mdio-mux"
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- mdio-parent-bus: a phandle to EMAC mdio
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- one child mdio for the integrated mdio with the compatible
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"allwinner,sun8i-h3-mdio-internal"
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- one child mdio for the external mdio if present (V3s have none)
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Required properties for the mdio-mux children node:
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- reg: 1 for internal MDIO bus, 2 for external MDIO bus
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The following compatibles require a PHY node representing the integrated
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PHY, under the integrated MDIO bus node if an mdio-mux node is used:
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- "allwinner,sun8i-h3-emac",
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- "allwinner,sun8i-v3s-emac":
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Additional information regarding generic multiplexer properties can be found
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at Documentation/devicetree/bindings/net/mdio-mux.txt
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Required properties of the integrated phy node:
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- clocks: a phandle to the reference clock for the EPHY
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- resets: a phandle to the reset control for the EPHY
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- Must be a child of the integrated mdio
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Example with integrated PHY:
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emac: ethernet@1c0b000 {
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compatible = "allwinner,sun8i-h3-emac";
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syscon = <&syscon>;
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reg = <0x01c0b000 0x104>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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reset-names = "stmmaceth";
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clocks = <&ccu CLK_BUS_EMAC>;
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clock-names = "stmmaceth";
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phy-handle = <&int_mii_phy>;
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phy-mode = "mii";
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allwinner,leds-active-low;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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mdio-mux {
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compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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mdio-parent-bus = <&mdio>;
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int_mdio: mdio@1 {
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compatible = "allwinner,sun8i-h3-mdio-internal";
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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int_mii_phy: ethernet-phy@1 {
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reg = <1>;
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clocks = <&ccu CLK_BUS_EPHY>;
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resets = <&ccu RST_BUS_EPHY>;
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phy-is-integrated;
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};
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};
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ext_mdio: mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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Example with external PHY:
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emac: ethernet@1c0b000 {
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compatible = "allwinner,sun8i-h3-emac";
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syscon = <&syscon>;
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reg = <0x01c0b000 0x104>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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reset-names = "stmmaceth";
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clocks = <&ccu CLK_BUS_EMAC>;
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clock-names = "stmmaceth";
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phy-handle = <&ext_rgmii_phy>;
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phy-mode = "rgmii";
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allwinner,leds-active-low;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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};
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mdio-mux {
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compatible = "allwinner,sun8i-h3-mdio-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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mdio-parent-bus = <&mdio>;
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int_mdio: mdio@1 {
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compatible = "allwinner,sun8i-h3-mdio-internal";
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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int_mii_phy: ethernet-phy@1 {
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reg = <1>;
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clocks = <&ccu CLK_BUS_EPHY>;
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resets = <&ccu RST_BUS_EPHY>;
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};
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};
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ext_mdio: mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ext_rgmii_phy: ethernet-phy@1 {
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reg = <1>;
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};
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}:
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};
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};
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Example with SoC without integrated PHY
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emac: ethernet@1c0b000 {
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compatible = "allwinner,sun8i-a83t-emac";
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syscon = <&syscon>;
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reg = <0x01c0b000 0x104>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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resets = <&ccu RST_BUS_EMAC>;
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reset-names = "stmmaceth";
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clocks = <&ccu CLK_BUS_EMAC>;
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clock-names = "stmmaceth";
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phy-handle = <&ext_rgmii_phy>;
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phy-mode = "rgmii";
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mdio: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ext_rgmii_phy: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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