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Add irq_chip support for both IPI and "normal" interrupts of the CIU3 controller. Document the device tree binding for the CIU3. Some functions are non-static as they will be used by follow-on support for MSI-X. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
28 lines
791 B
Plaintext
28 lines
791 B
Plaintext
* Central Interrupt Unit v3
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Properties:
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- compatible: "cavium,octeon-7890-ciu3"
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Compatibility with 78XX and 73XX SOCs.
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- interrupt-controller: This is an interrupt controller.
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- reg: The base address of the CIU's register bank.
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- #interrupt-cells: Must be <2>. The first cell is source number.
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The second cell indicates the triggering semantics, and may have a
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value of either 4 for level semantics, or 1 for edge semantics.
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Example:
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interrupt-controller@1010000000000 {
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compatible = "cavium,octeon-7890-ciu3";
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interrupt-controller;
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/* Interrupts are specified by two parts:
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* 1) Source number (20 significant bits)
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* 2) Trigger type: (4 == level, 1 == edge)
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*/
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x10100 0x00000000 0x0 0xb0000000>;
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};
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