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[ Upstream commit 439c7183e5b97952bba1747f5ffc4dea45a6a18b ] UARTs on TI SoCs prior to J7200 don't provide independent control over RX FIFO not empty interrupt (RHR_IT) and RX timeout interrupt. Starting with J7200 SoC, its possible to disable RHR_IT independent of RX timeout interrupt using bit 2 of IER2 register. So disable RHR_IT once RX DMA is started so as to avoid spurious interrupt being raised when data is in the RX FIFO but is yet to be drained by DMA (a known errata in older SoCs). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20201029051930.7097-1-vigneshr@ti.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Sasha Levin <sashal@kernel.org> |
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| .. | ||
| 8250_accent.c | ||
| 8250_acorn.c | ||
| 8250_aspeed_vuart.c | ||
| 8250_bcm2835aux.c | ||
| 8250_boca.c | ||
| 8250_core.c | ||
| 8250_dma.c | ||
| 8250_dw.c | ||
| 8250_dwlib.c | ||
| 8250_dwlib.h | ||
| 8250_early.c | ||
| 8250_em.c | ||
| 8250_exar_st16c554.c | ||
| 8250_exar.c | ||
| 8250_fintek.c | ||
| 8250_fourport.c | ||
| 8250_fsl.c | ||
| 8250_gsc.c | ||
| 8250_hp300.c | ||
| 8250_hub6.c | ||
| 8250_ingenic.c | ||
| 8250_ioc3.c | ||
| 8250_lpc18xx.c | ||
| 8250_lpss.c | ||
| 8250_men_mcb.c | ||
| 8250_mid.c | ||
| 8250_mtk.c | ||
| 8250_of.c | ||
| 8250_omap.c | ||
| 8250_pci.c | ||
| 8250_pnp.c | ||
| 8250_port.c | ||
| 8250_pxa.c | ||
| 8250_tegra.c | ||
| 8250_uniphier.c | ||
| 8250.h | ||
| Kconfig | ||
| Makefile | ||
| serial_cs.c | ||