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a0668cdc15
Currently we have a fair bit of rather fiddly code to manage the various kmem_caches used to store page tables of various levels. We generally have two caches holding some combination of PGD, PUD and PMD tables, plus several more for the special hugepage pagetables. This patch cleans this all up by taking a different approach. Rather than the caches being designated as for PUDs or for hugeptes for 16M pages, the caches are simply allocated to be a specific size. Thus sharing of caches between different types/levels of pagetables happens naturally. The pagetable size, where needed, is passed around encoded in the same way as {PGD,PUD,PMD}_INDEX_SIZE; that is n where the pagetable contains 2^n pointers. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
346 lines
9.2 KiB
C
346 lines
9.2 KiB
C
/*
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* This file contains common routines for dealing with free of page tables
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* Along with common page table handling code
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*
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* Derived from arch/powerpc/mm/tlb_64.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* Dave Engebretsen <engebret@us.ibm.com>
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* Rework for PPC64 port.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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#include "mmu_decl.h"
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DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
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#ifdef CONFIG_SMP
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/*
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* Handle batching of page table freeing on SMP. Page tables are
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* queued up and send to be freed later by RCU in order to avoid
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* freeing a page table page that is being walked without locks
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*/
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static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
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static unsigned long pte_freelist_forced_free;
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struct pte_freelist_batch
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{
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struct rcu_head rcu;
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unsigned int index;
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unsigned long tables[0];
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};
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#define PTE_FREELIST_SIZE \
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((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
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/ sizeof(unsigned long))
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static void pte_free_smp_sync(void *arg)
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{
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/* Do nothing, just ensure we sync with all CPUs */
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}
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/* This is only called when we are critically out of memory
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* (and fail to get a page in pte_free_tlb).
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*/
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static void pgtable_free_now(void *table, unsigned shift)
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{
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pte_freelist_forced_free++;
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smp_call_function(pte_free_smp_sync, NULL, 1);
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pgtable_free(table, shift);
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}
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static void pte_free_rcu_callback(struct rcu_head *head)
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{
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struct pte_freelist_batch *batch =
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container_of(head, struct pte_freelist_batch, rcu);
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unsigned int i;
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for (i = 0; i < batch->index; i++) {
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void *table = (void *)(batch->tables[i] & ~MAX_PGTABLE_INDEX_SIZE);
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unsigned shift = batch->tables[i] & MAX_PGTABLE_INDEX_SIZE;
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pgtable_free(table, shift);
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}
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free_page((unsigned long)batch);
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}
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static void pte_free_submit(struct pte_freelist_batch *batch)
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{
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INIT_RCU_HEAD(&batch->rcu);
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call_rcu(&batch->rcu, pte_free_rcu_callback);
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}
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void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
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{
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/* This is safe since tlb_gather_mmu has disabled preemption */
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struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
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unsigned long pgf;
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if (atomic_read(&tlb->mm->mm_users) < 2 ||
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cpumask_equal(mm_cpumask(tlb->mm), cpumask_of(smp_processor_id()))){
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pgtable_free(table, shift);
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return;
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}
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if (*batchp == NULL) {
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*batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
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if (*batchp == NULL) {
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pgtable_free_now(table, shift);
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return;
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}
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(*batchp)->index = 0;
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}
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BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
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pgf = (unsigned long)table | shift;
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(*batchp)->tables[(*batchp)->index++] = pgf;
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if ((*batchp)->index == PTE_FREELIST_SIZE) {
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pte_free_submit(*batchp);
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*batchp = NULL;
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}
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}
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void pte_free_finish(void)
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{
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/* This is safe since tlb_gather_mmu has disabled preemption */
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struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
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if (*batchp == NULL)
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return;
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pte_free_submit(*batchp);
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*batchp = NULL;
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}
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#endif /* CONFIG_SMP */
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static inline int is_exec_fault(void)
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{
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return current->thread.regs && TRAP(current->thread.regs) == 0x400;
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}
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/* We only try to do i/d cache coherency on stuff that looks like
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* reasonably "normal" PTEs. We currently require a PTE to be present
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* and we avoid _PAGE_SPECIAL and _PAGE_NO_CACHE. We also only do that
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* on userspace PTEs
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*/
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static inline int pte_looks_normal(pte_t pte)
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{
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return (pte_val(pte) &
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(_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE | _PAGE_USER)) ==
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(_PAGE_PRESENT | _PAGE_USER);
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}
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struct page * maybe_pte_to_page(pte_t pte)
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{
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unsigned long pfn = pte_pfn(pte);
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struct page *page;
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if (unlikely(!pfn_valid(pfn)))
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return NULL;
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page = pfn_to_page(pfn);
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if (PageReserved(page))
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return NULL;
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return page;
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}
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#if defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0
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/* Server-style MMU handles coherency when hashing if HW exec permission
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* is supposed per page (currently 64-bit only). If not, then, we always
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* flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
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* support falls into the same category.
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*/
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static pte_t set_pte_filter(pte_t pte, unsigned long addr)
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{
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pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
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if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
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cpu_has_feature(CPU_FTR_NOEXECUTE))) {
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struct page *pg = maybe_pte_to_page(pte);
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if (!pg)
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return pte;
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if (!test_bit(PG_arch_1, &pg->flags)) {
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#ifdef CONFIG_8xx
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/* On 8xx, cache control instructions (particularly
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* "dcbst" from flush_dcache_icache) fault as write
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* operation if there is an unpopulated TLB entry
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* for the address in question. To workaround that,
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* we invalidate the TLB here, thus avoiding dcbst
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* misbehaviour.
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*/
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/* 8xx doesn't care about PID, size or ind args */
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_tlbil_va(addr, 0, 0, 0);
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#endif /* CONFIG_8xx */
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flush_dcache_icache_page(pg);
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set_bit(PG_arch_1, &pg->flags);
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}
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}
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return pte;
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}
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static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
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int dirty)
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{
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return pte;
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}
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#else /* defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0 */
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/* Embedded type MMU with HW exec support. This is a bit more complicated
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* as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
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* instead we "filter out" the exec permission for non clean pages.
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*/
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static pte_t set_pte_filter(pte_t pte, unsigned long addr)
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{
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struct page *pg;
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/* No exec permission in the first place, move on */
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if (!(pte_val(pte) & _PAGE_EXEC) || !pte_looks_normal(pte))
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return pte;
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/* If you set _PAGE_EXEC on weird pages you're on your own */
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pg = maybe_pte_to_page(pte);
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if (unlikely(!pg))
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return pte;
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/* If the page clean, we move on */
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if (test_bit(PG_arch_1, &pg->flags))
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return pte;
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/* If it's an exec fault, we flush the cache and make it clean */
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if (is_exec_fault()) {
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flush_dcache_icache_page(pg);
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set_bit(PG_arch_1, &pg->flags);
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return pte;
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}
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/* Else, we filter out _PAGE_EXEC */
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return __pte(pte_val(pte) & ~_PAGE_EXEC);
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}
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static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
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int dirty)
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{
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struct page *pg;
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/* So here, we only care about exec faults, as we use them
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* to recover lost _PAGE_EXEC and perform I$/D$ coherency
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* if necessary. Also if _PAGE_EXEC is already set, same deal,
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* we just bail out
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*/
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if (dirty || (pte_val(pte) & _PAGE_EXEC) || !is_exec_fault())
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return pte;
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#ifdef CONFIG_DEBUG_VM
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/* So this is an exec fault, _PAGE_EXEC is not set. If it was
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* an error we would have bailed out earlier in do_page_fault()
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* but let's make sure of it
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*/
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if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
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return pte;
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#endif /* CONFIG_DEBUG_VM */
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/* If you set _PAGE_EXEC on weird pages you're on your own */
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pg = maybe_pte_to_page(pte);
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if (unlikely(!pg))
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goto bail;
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/* If the page is already clean, we move on */
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if (test_bit(PG_arch_1, &pg->flags))
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goto bail;
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/* Clean the page and set PG_arch_1 */
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flush_dcache_icache_page(pg);
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set_bit(PG_arch_1, &pg->flags);
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bail:
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return __pte(pte_val(pte) | _PAGE_EXEC);
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}
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#endif /* !(defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0) */
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/*
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* set_pte stores a linux PTE into the linux page table.
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*/
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void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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pte_t pte)
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{
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#ifdef CONFIG_DEBUG_VM
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WARN_ON(pte_present(*ptep));
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#endif
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/* Note: mm->context.id might not yet have been assigned as
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* this context might not have been activated yet when this
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* is called.
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*/
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pte = set_pte_filter(pte, addr);
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/* Perform the setting of the PTE */
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__set_pte_at(mm, addr, ptep, pte, 0);
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}
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/*
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* This is called when relaxing access to a PTE. It's also called in the page
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* fault path when we don't hit any of the major fault cases, ie, a minor
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* update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
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* handled those two for us, we additionally deal with missing execute
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* permission here on some processors
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*/
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int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
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pte_t *ptep, pte_t entry, int dirty)
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{
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int changed;
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entry = set_access_flags_filter(entry, vma, dirty);
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changed = !pte_same(*(ptep), entry);
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if (changed) {
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if (!(vma->vm_flags & VM_HUGETLB))
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assert_pte_locked(vma->vm_mm, address);
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__ptep_set_access_flags(ptep, entry);
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flush_tlb_page_nohash(vma, address);
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}
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return changed;
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}
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#ifdef CONFIG_DEBUG_VM
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void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
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{
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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if (mm == &init_mm)
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return;
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pgd = mm->pgd + pgd_index(addr);
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BUG_ON(pgd_none(*pgd));
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pud = pud_offset(pgd, addr);
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BUG_ON(pud_none(*pud));
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pmd = pmd_offset(pud, addr);
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BUG_ON(!pmd_present(*pmd));
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assert_spin_locked(pte_lockptr(mm, pmd));
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}
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#endif /* CONFIG_DEBUG_VM */
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