mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 08:46:49 +07:00
64082568dd
I seem to have omitted the LVDS clock from the R8A77970 CPG/MSSR support
patch for some reason -- add it back...
Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.
Fixes: 8d46e28fb5 ("clk: renesas: cpg-mssr: Add R8A77970 support")
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
201 lines
6.4 KiB
C
201 lines
6.4 KiB
C
/*
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* r8a77970 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2017 Cogent Embedded Inc.
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*
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* Based on r8a7795-cpg-mssr.c
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*
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* Copyright (C) 2015 Glider bvba
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/soc/renesas/rcar-rst.h>
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#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_EXTALR,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL3,
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CLK_PLL1_DIV2,
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CLK_PLL1_DIV4,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
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/* Core Clock Outputs */
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DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
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DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1),
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DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1),
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DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
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DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
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DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
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DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1),
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DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
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};
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static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
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DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
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DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
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DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
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DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
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DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
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DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
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DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
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DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
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DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
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DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
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DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
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DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
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DEF_MOD("rwdt", 402, R8A77970_CLK_R),
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DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
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DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
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DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1),
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DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1),
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DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1),
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DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1),
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DEF_MOD("thermal", 522, R8A77970_CLK_CP),
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DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
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DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
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DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
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DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
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DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
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DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
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DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
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DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
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DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
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DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
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DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
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DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
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DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
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DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
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DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
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DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
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DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
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DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
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DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
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DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
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DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
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DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
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DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
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};
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static const unsigned int r8a77970_crit_mod_clks[] __initconst = {
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MOD_CLK_ID(408), /* INTC-AP (GIC) */
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};
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/*
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* CPG Clock Data
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*/
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/*
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* MD EXTAL PLL0 PLL1 PLL3
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* 14 13 19 (MHz)
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*-------------------------------------------------
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* 0 0 0 16.66 x 1 x192 x192 x96
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* 0 0 1 16.66 x 1 x192 x192 x80
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* 0 1 0 20 x 1 x160 x160 x80
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* 0 1 1 20 x 1 x160 x160 x66
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* 1 0 0 27 / 2 x236 x236 x118
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* 1 0 1 27 / 2 x236 x236 x98
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* 1 1 0 33.33 / 2 x192 x192 x96
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* 1 1 1 33.33 / 2 x192 x192 x80
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
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(((md) & BIT(13)) >> 12) | \
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(((md) & BIT(19)) >> 19))
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static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
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/* EXTAL div PLL1 mult/div PLL3 mult/div */
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{ 1, 192, 1, 96, 1, },
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{ 1, 192, 1, 80, 1, },
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{ 1, 160, 1, 80, 1, },
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{ 1, 160, 1, 66, 1, },
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{ 2, 236, 1, 118, 1, },
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{ 2, 236, 1, 98, 1, },
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{ 2, 192, 1, 96, 1, },
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{ 2, 192, 1, 80, 1, },
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};
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static int __init r8a77970_cpg_mssr_init(struct device *dev)
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{
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const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
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u32 cpg_mode;
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int error;
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error = rcar_rst_read_mode_pins(&cpg_mode);
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if (error)
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return error;
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cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
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}
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const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
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/* Core Clocks */
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.core_clks = r8a77970_core_clks,
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.num_core_clks = ARRAY_SIZE(r8a77970_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r8a77970_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r8a77970_mod_clks),
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.num_hw_mod_clks = 12 * 32,
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/* Critical Module Clocks */
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.crit_mod_clks = r8a77970_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r8a77970_crit_mod_clks),
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/* Callbacks */
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.init = r8a77970_cpg_mssr_init,
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.cpg_clk_register = rcar_gen3_cpg_clk_register,
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};
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