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commit 84fe2cab48 ("cpu_cooling: Drop static-power related stuff")
removed support for static-power in kernel, but it missed reflecting the
same in documentation. Remove the static power related documentation
bits as well.
Reported-by: Javi Merino <javi.merino@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
93 lines
3.8 KiB
Plaintext
93 lines
3.8 KiB
Plaintext
CPU cooling APIs How To
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===================================
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Written by Amit Daniel Kachhap <amit.kachhap@linaro.org>
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Updated: 6 Jan 2015
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Copyright (c) 2012 Samsung Electronics Co., Ltd(http://www.samsung.com)
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0. Introduction
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The generic cpu cooling(freq clipping) provides registration/unregistration APIs
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to the caller. The binding of the cooling devices to the trip point is left for
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the user. The registration APIs returns the cooling device pointer.
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1. cpu cooling APIs
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1.1 cpufreq registration/unregistration APIs
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1.1.1 struct thermal_cooling_device *cpufreq_cooling_register(
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struct cpumask *clip_cpus)
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This interface function registers the cpufreq cooling device with the name
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"thermal-cpufreq-%x". This api can support multiple instances of cpufreq
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cooling devices.
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clip_cpus: cpumask of cpus where the frequency constraints will happen.
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1.1.2 struct thermal_cooling_device *of_cpufreq_cooling_register(
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struct cpufreq_policy *policy)
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This interface function registers the cpufreq cooling device with
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the name "thermal-cpufreq-%x" linking it with a device tree node, in
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order to bind it via the thermal DT code. This api can support multiple
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instances of cpufreq cooling devices.
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policy: CPUFreq policy.
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1.1.3 void cpufreq_cooling_unregister(struct thermal_cooling_device *cdev)
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This interface function unregisters the "thermal-cpufreq-%x" cooling device.
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cdev: Cooling device pointer which has to be unregistered.
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2. Power models
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The power API registration functions provide a simple power model for
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CPUs. The current power is calculated as dynamic power (static power isn't
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supported currently). This power model requires that the operating-points of
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the CPUs are registered using the kernel's opp library and the
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`cpufreq_frequency_table` is assigned to the `struct device` of the
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cpu. If you are using CONFIG_CPUFREQ_DT then the
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`cpufreq_frequency_table` should already be assigned to the cpu
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device.
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The dynamic power consumption of a processor depends on many factors.
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For a given processor implementation the primary factors are:
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- The time the processor spends running, consuming dynamic power, as
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compared to the time in idle states where dynamic consumption is
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negligible. Herein we refer to this as 'utilisation'.
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- The voltage and frequency levels as a result of DVFS. The DVFS
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level is a dominant factor governing power consumption.
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- In running time the 'execution' behaviour (instruction types, memory
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access patterns and so forth) causes, in most cases, a second order
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variation. In pathological cases this variation can be significant,
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but typically it is of a much lesser impact than the factors above.
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A high level dynamic power consumption model may then be represented as:
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Pdyn = f(run) * Voltage^2 * Frequency * Utilisation
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f(run) here represents the described execution behaviour and its
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result has a units of Watts/Hz/Volt^2 (this often expressed in
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mW/MHz/uVolt^2)
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The detailed behaviour for f(run) could be modelled on-line. However,
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in practice, such an on-line model has dependencies on a number of
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implementation specific processor support and characterisation
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factors. Therefore, in initial implementation that contribution is
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represented as a constant coefficient. This is a simplification
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consistent with the relative contribution to overall power variation.
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In this simplified representation our model becomes:
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Pdyn = Capacitance * Voltage^2 * Frequency * Utilisation
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Where `capacitance` is a constant that represents an indicative
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running time dynamic power coefficient in fundamental units of
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mW/MHz/uVolt^2. Typical values for mobile CPUs might lie in range
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from 100 to 500. For reference, the approximate values for the SoC in
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ARM's Juno Development Platform are 530 for the Cortex-A57 cluster and
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140 for the Cortex-A53 cluster.
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