mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 12:46:47 +07:00
c9fcf007f1
Export the following sh7377 multimedia hardware blocks using UIO: VPU, VEU[0-3], JPU and SPU2[0-1] Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
470 lines
9.9 KiB
C
470 lines
9.9 KiB
C
/*
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* sh7377 processor support
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2008 Yoshihiro Shimoda
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/uio_driver.h>
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#include <linux/delay.h>
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#include <linux/input.h>
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#include <linux/io.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_intc.h>
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#include <linux/sh_timer.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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/* SCIFA0 */
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xe6c40000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0xc00), evt2irq(0xc00),
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evt2irq(0xc00), evt2irq(0xc00) },
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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/* SCIFA1 */
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static struct plat_sci_port scif1_platform_data = {
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.mapbase = 0xe6c50000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0xc20), evt2irq(0xc20),
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evt2irq(0xc20), evt2irq(0xc20) },
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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/* SCIFA2 */
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static struct plat_sci_port scif2_platform_data = {
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.mapbase = 0xe6c60000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0xc40), evt2irq(0xc40),
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evt2irq(0xc40), evt2irq(0xc40) },
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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/* SCIFA3 */
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static struct plat_sci_port scif3_platform_data = {
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.mapbase = 0xe6c70000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0xc60), evt2irq(0xc60),
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evt2irq(0xc60), evt2irq(0xc60) },
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};
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static struct platform_device scif3_device = {
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.name = "sh-sci",
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.id = 3,
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.dev = {
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.platform_data = &scif3_platform_data,
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},
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};
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/* SCIFA4 */
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static struct plat_sci_port scif4_platform_data = {
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.mapbase = 0xe6c80000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0xd20), evt2irq(0xd20),
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evt2irq(0xd20), evt2irq(0xd20) },
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};
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static struct platform_device scif4_device = {
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.name = "sh-sci",
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.id = 4,
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.dev = {
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.platform_data = &scif4_platform_data,
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},
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};
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/* SCIFA5 */
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static struct plat_sci_port scif5_platform_data = {
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.mapbase = 0xe6cb0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { evt2irq(0xd40), evt2irq(0xd40),
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evt2irq(0xd40), evt2irq(0xd40) },
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};
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static struct platform_device scif5_device = {
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.name = "sh-sci",
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.id = 5,
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.dev = {
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.platform_data = &scif5_platform_data,
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},
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};
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/* SCIFA6 */
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static struct plat_sci_port scif6_platform_data = {
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.mapbase = 0xe6cc0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
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intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
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};
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static struct platform_device scif6_device = {
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.name = "sh-sci",
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.id = 6,
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.dev = {
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.platform_data = &scif6_platform_data,
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},
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};
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/* SCIFB */
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static struct plat_sci_port scif7_platform_data = {
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.mapbase = 0xe6c30000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFB,
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.irqs = { evt2irq(0xd60), evt2irq(0xd60),
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evt2irq(0xd60), evt2irq(0xd60) },
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};
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static struct platform_device scif7_device = {
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.name = "sh-sci",
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.id = 7,
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.dev = {
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.platform_data = &scif7_platform_data,
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},
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};
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static struct sh_timer_config cmt10_platform_data = {
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.name = "CMT10",
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.channel_offset = 0x10,
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.timer_bit = 0,
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.clockevent_rating = 125,
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.clocksource_rating = 125,
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};
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static struct resource cmt10_resources[] = {
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[0] = {
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.name = "CMT10",
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.start = 0xe6138010,
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.end = 0xe613801b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0xb00), /* CMT1_CMT10 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cmt10_device = {
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.name = "sh_cmt",
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.id = 10,
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.dev = {
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.platform_data = &cmt10_platform_data,
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},
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.resource = cmt10_resources,
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.num_resources = ARRAY_SIZE(cmt10_resources),
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};
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/* VPU */
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static struct uio_info vpu_platform_data = {
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.name = "VPU5HG",
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.version = "0",
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.irq = intcs_evt2irq(0x980),
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};
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static struct resource vpu_resources[] = {
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[0] = {
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.name = "VPU",
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.start = 0xfe900000,
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.end = 0xfe900157,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device vpu_device = {
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.name = "uio_pdrv_genirq",
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.id = 0,
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.dev = {
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.platform_data = &vpu_platform_data,
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},
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.resource = vpu_resources,
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.num_resources = ARRAY_SIZE(vpu_resources),
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};
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/* VEU0 */
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static struct uio_info veu0_platform_data = {
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.name = "VEU0",
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.version = "0",
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.irq = intcs_evt2irq(0x700),
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};
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static struct resource veu0_resources[] = {
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[0] = {
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.name = "VEU0",
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.start = 0xfe920000,
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.end = 0xfe9200cb,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device veu0_device = {
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.name = "uio_pdrv_genirq",
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.id = 1,
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.dev = {
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.platform_data = &veu0_platform_data,
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},
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.resource = veu0_resources,
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.num_resources = ARRAY_SIZE(veu0_resources),
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};
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/* VEU1 */
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static struct uio_info veu1_platform_data = {
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.name = "VEU1",
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.version = "0",
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.irq = intcs_evt2irq(0x720),
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};
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static struct resource veu1_resources[] = {
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[0] = {
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.name = "VEU1",
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.start = 0xfe924000,
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.end = 0xfe9240cb,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device veu1_device = {
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.name = "uio_pdrv_genirq",
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.id = 2,
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.dev = {
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.platform_data = &veu1_platform_data,
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},
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.resource = veu1_resources,
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.num_resources = ARRAY_SIZE(veu1_resources),
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};
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/* VEU2 */
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static struct uio_info veu2_platform_data = {
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.name = "VEU2",
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.version = "0",
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.irq = intcs_evt2irq(0x740),
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};
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static struct resource veu2_resources[] = {
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[0] = {
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.name = "VEU2",
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.start = 0xfe928000,
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.end = 0xfe928307,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device veu2_device = {
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.name = "uio_pdrv_genirq",
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.id = 3,
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.dev = {
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.platform_data = &veu2_platform_data,
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},
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.resource = veu2_resources,
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.num_resources = ARRAY_SIZE(veu2_resources),
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};
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/* VEU3 */
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static struct uio_info veu3_platform_data = {
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.name = "VEU3",
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.version = "0",
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.irq = intcs_evt2irq(0x760),
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};
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static struct resource veu3_resources[] = {
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[0] = {
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.name = "VEU3",
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.start = 0xfe92c000,
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.end = 0xfe92c307,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device veu3_device = {
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.name = "uio_pdrv_genirq",
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.id = 4,
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.dev = {
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.platform_data = &veu3_platform_data,
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},
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.resource = veu3_resources,
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.num_resources = ARRAY_SIZE(veu3_resources),
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};
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/* JPU */
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static struct uio_info jpu_platform_data = {
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.name = "JPU",
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.version = "0",
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.irq = intcs_evt2irq(0x560),
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};
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static struct resource jpu_resources[] = {
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[0] = {
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.name = "JPU",
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.start = 0xfe980000,
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.end = 0xfe9902d3,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device jpu_device = {
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.name = "uio_pdrv_genirq",
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.id = 5,
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.dev = {
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.platform_data = &jpu_platform_data,
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},
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.resource = jpu_resources,
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.num_resources = ARRAY_SIZE(jpu_resources),
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};
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/* SPU2DSP0 */
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static struct uio_info spu0_platform_data = {
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.name = "SPU2DSP0",
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.version = "0",
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.irq = evt2irq(0x1800),
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};
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static struct resource spu0_resources[] = {
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[0] = {
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.name = "SPU2DSP0",
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.start = 0xfe200000,
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.end = 0xfe2fffff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device spu0_device = {
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.name = "uio_pdrv_genirq",
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.id = 6,
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.dev = {
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.platform_data = &spu0_platform_data,
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},
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.resource = spu0_resources,
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.num_resources = ARRAY_SIZE(spu0_resources),
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};
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/* SPU2DSP1 */
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static struct uio_info spu1_platform_data = {
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.name = "SPU2DSP1",
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.version = "0",
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.irq = evt2irq(0x1820),
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};
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static struct resource spu1_resources[] = {
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[0] = {
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.name = "SPU2DSP1",
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.start = 0xfe300000,
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.end = 0xfe3fffff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device spu1_device = {
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.name = "uio_pdrv_genirq",
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.id = 7,
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.dev = {
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.platform_data = &spu1_platform_data,
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},
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.resource = spu1_resources,
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.num_resources = ARRAY_SIZE(spu1_resources),
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};
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static struct platform_device *sh7377_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&scif3_device,
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&scif4_device,
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&scif5_device,
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&scif6_device,
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&scif7_device,
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&cmt10_device,
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};
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static struct platform_device *sh7377_devices[] __initdata = {
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&vpu_device,
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&veu0_device,
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&veu1_device,
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&veu2_device,
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&veu3_device,
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&jpu_device,
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&spu0_device,
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&spu1_device,
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};
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void __init sh7377_add_standard_devices(void)
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{
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platform_add_devices(sh7377_early_devices,
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ARRAY_SIZE(sh7377_early_devices));
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platform_add_devices(sh7377_devices,
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ARRAY_SIZE(sh7377_devices));
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}
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR3_CMT1 (1 << 29)
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void __init sh7377_add_early_devices(void)
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{
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/* enable clock to CMT1 */
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__raw_writel(__raw_readl(SMSTPCR3) & ~SMSTPCR3_CMT1, SMSTPCR3);
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early_platform_add_devices(sh7377_early_devices,
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ARRAY_SIZE(sh7377_early_devices));
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}
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