mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 19:35:00 +07:00
0a886f5952
It adds the initial ZTE VOU display controller DRM driver. There are still some features to be added, like overlay plane, scaling, and more output devices support. But it's already useful with dual CRTCs and HDMI monitor working. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
92 lines
2.8 KiB
C
92 lines
2.8 KiB
C
/*
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* Copyright 2016 Linaro Ltd.
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* Copyright 2016 ZTE Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ZX_PLANE_REGS_H__
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#define __ZX_PLANE_REGS_H__
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/* GL registers */
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#define GL_CTRL0 0x00
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#define GL_UPDATE BIT(5)
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#define GL_CTRL1 0x04
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#define GL_DATA_FMT_SHIFT 0
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#define GL_DATA_FMT_MASK (0xf << GL_DATA_FMT_SHIFT)
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#define GL_FMT_ARGB8888 0
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#define GL_FMT_RGB888 1
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#define GL_FMT_RGB565 2
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#define GL_FMT_ARGB1555 3
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#define GL_FMT_ARGB4444 4
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#define GL_CTRL2 0x08
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#define GL_GLOBAL_ALPHA_SHIFT 8
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#define GL_GLOBAL_ALPHA_MASK (0xff << GL_GLOBAL_ALPHA_SHIFT)
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#define GL_CTRL3 0x0c
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#define GL_SCALER_BYPASS_MODE BIT(0)
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#define GL_STRIDE 0x18
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#define GL_ADDR 0x1c
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#define GL_SRC_SIZE 0x38
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#define GL_SRC_W_SHIFT 16
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#define GL_SRC_W_MASK (0x3fff << GL_SRC_W_SHIFT)
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#define GL_SRC_H_SHIFT 0
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#define GL_SRC_H_MASK (0x3fff << GL_SRC_H_SHIFT)
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#define GL_POS_START 0x9c
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#define GL_POS_END 0xa0
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#define GL_POS_X_SHIFT 16
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#define GL_POS_X_MASK (0x1fff << GL_POS_X_SHIFT)
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#define GL_POS_Y_SHIFT 0
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#define GL_POS_Y_MASK (0x1fff << GL_POS_Y_SHIFT)
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#define GL_SRC_W(x) (((x) << GL_SRC_W_SHIFT) & GL_SRC_W_MASK)
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#define GL_SRC_H(x) (((x) << GL_SRC_H_SHIFT) & GL_SRC_H_MASK)
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#define GL_POS_X(x) (((x) << GL_POS_X_SHIFT) & GL_POS_X_MASK)
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#define GL_POS_Y(x) (((x) << GL_POS_Y_SHIFT) & GL_POS_Y_MASK)
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/* CSC registers */
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#define CSC_CTRL0 0x30
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#define CSC_COV_MODE_SHIFT 16
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#define CSC_COV_MODE_MASK (0xffff << CSC_COV_MODE_SHIFT)
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#define CSC_BT601_IMAGE_RGB2YCBCR 0
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#define CSC_BT601_IMAGE_YCBCR2RGB 1
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#define CSC_BT601_VIDEO_RGB2YCBCR 2
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#define CSC_BT601_VIDEO_YCBCR2RGB 3
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#define CSC_BT709_IMAGE_RGB2YCBCR 4
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#define CSC_BT709_IMAGE_YCBCR2RGB 5
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#define CSC_BT709_VIDEO_RGB2YCBCR 6
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#define CSC_BT709_VIDEO_YCBCR2RGB 7
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#define CSC_BT2020_IMAGE_RGB2YCBCR 8
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#define CSC_BT2020_IMAGE_YCBCR2RGB 9
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#define CSC_BT2020_VIDEO_RGB2YCBCR 10
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#define CSC_BT2020_VIDEO_YCBCR2RGB 11
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#define CSC_WORK_ENABLE BIT(0)
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/* RSZ registers */
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#define RSZ_SRC_CFG 0x00
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#define RSZ_DEST_CFG 0x04
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#define RSZ_ENABLE_CFG 0x14
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#define RSZ_VER_SHIFT 16
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#define RSZ_VER_MASK (0xffff << RSZ_VER_SHIFT)
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#define RSZ_HOR_SHIFT 0
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#define RSZ_HOR_MASK (0xffff << RSZ_HOR_SHIFT)
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#define RSZ_VER(x) (((x) << RSZ_VER_SHIFT) & RSZ_VER_MASK)
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#define RSZ_HOR(x) (((x) << RSZ_HOR_SHIFT) & RSZ_HOR_MASK)
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/* HBSC registers */
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#define HBSC_SATURATION 0x00
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#define HBSC_HUE 0x04
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#define HBSC_BRIGHT 0x08
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#define HBSC_CONTRAST 0x0c
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#define HBSC_THRESHOLD_COL1 0x10
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#define HBSC_THRESHOLD_COL2 0x14
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#define HBSC_THRESHOLD_COL3 0x18
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#define HBSC_CTRL0 0x28
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#define HBSC_CTRL_EN BIT(2)
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#endif /* __ZX_PLANE_REGS_H__ */
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