mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 13:36:48 +07:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
337 lines
7.4 KiB
C
337 lines
7.4 KiB
C
/* internal Peripherals Register address define */
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/* CPU: H8/306x */
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#if !defined(__REGS_H8S267x__)
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#define __REGS_H8S267x__
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#if defined(__KERNEL__)
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#define DASTCR 0xFEE01A
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#define DADR0 0xFFFFA4
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#define DADR1 0xFFFFA5
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#define DACR01 0xFFFFA6
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#define DADR2 0xFFFFA8
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#define DADR3 0xFFFFA9
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#define DACR23 0xFFFFAA
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#define ADDRA 0xFFFF90
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#define ADDRAH 0xFFFF90
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#define ADDRAL 0xFFFF91
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#define ADDRB 0xFFFF92
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#define ADDRBH 0xFFFF92
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#define ADDRBL 0xFFFF93
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#define ADDRC 0xFFFF94
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#define ADDRCH 0xFFFF94
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#define ADDRCL 0xFFFF95
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#define ADDRD 0xFFFF96
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#define ADDRDH 0xFFFF96
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#define ADDRDL 0xFFFF97
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#define ADDRE 0xFFFF98
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#define ADDREH 0xFFFF98
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#define ADDREL 0xFFFF99
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#define ADDRF 0xFFFF9A
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#define ADDRFH 0xFFFF9A
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#define ADDRFL 0xFFFF9B
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#define ADDRG 0xFFFF9C
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#define ADDRGH 0xFFFF9C
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#define ADDRGL 0xFFFF9D
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#define ADDRH 0xFFFF9E
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#define ADDRHH 0xFFFF9E
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#define ADDRHL 0xFFFF9F
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#define ADCSR 0xFFFFA0
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#define ADCR 0xFFFFA1
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#define ABWCR 0xFFFEC0
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#define ASTCR 0xFFFEC1
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#define WTCRAH 0xFFFEC2
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#define WTCRAL 0xFFFEC3
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#define WTCRBH 0xFFFEC4
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#define WTCRBL 0xFFFEC5
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#define RDNCR 0xFFFEC6
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#define CSACRH 0xFFFEC8
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#define CSACRL 0xFFFEC9
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#define BROMCRH 0xFFFECA
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#define BROMCRL 0xFFFECB
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#define BCR 0xFFFECC
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#define DRAMCR 0xFFFED0
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#define DRACCR 0xFFFED2
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#define REFCR 0xFFFED4
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#define RTCNT 0xFFFED6
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#define RTCOR 0xFFFED7
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#define MAR0AH 0xFFFEE0
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#define MAR0AL 0xFFFEE2
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#define IOAR0A 0xFFFEE4
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#define ETCR0A 0xFFFEE6
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#define MAR0BH 0xFFFEE8
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#define MAR0BL 0xFFFEEA
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#define IOAR0B 0xFFFEEC
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#define ETCR0B 0xFFFEEE
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#define MAR1AH 0xFFFEF0
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#define MAR1AL 0xFFFEF2
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#define IOAR1A 0xFFFEF4
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#define ETCR1A 0xFFFEF6
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#define MAR1BH 0xFFFEF8
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#define MAR1BL 0xFFFEFA
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#define IOAR1B 0xFFFEFC
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#define ETCR1B 0xFFFEFE
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#define DMAWER 0xFFFF20
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#define DMATCR 0xFFFF21
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#define DMACR0A 0xFFFF22
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#define DMACR0B 0xFFFF23
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#define DMACR1A 0xFFFF24
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#define DMACR1B 0xFFFF25
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#define DMABCRH 0xFFFF26
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#define DMABCRL 0xFFFF27
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#define EDSAR0 0xFFFDC0
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#define EDDAR0 0xFFFDC4
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#define EDTCR0 0xFFFDC8
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#define EDMDR0 0xFFFDCC
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#define EDMDR0H 0xFFFDCC
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#define EDMDR0L 0xFFFDCD
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#define EDACR0 0xFFFDCE
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#define EDSAR1 0xFFFDD0
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#define EDDAR1 0xFFFDD4
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#define EDTCR1 0xFFFDD8
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#define EDMDR1 0xFFFDDC
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#define EDMDR1H 0xFFFDDC
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#define EDMDR1L 0xFFFDDD
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#define EDACR1 0xFFFDDE
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#define EDSAR2 0xFFFDE0
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#define EDDAR2 0xFFFDE4
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#define EDTCR2 0xFFFDE8
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#define EDMDR2 0xFFFDEC
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#define EDMDR2H 0xFFFDEC
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#define EDMDR2L 0xFFFDED
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#define EDACR2 0xFFFDEE
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#define EDSAR3 0xFFFDF0
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#define EDDAR3 0xFFFDF4
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#define EDTCR3 0xFFFDF8
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#define EDMDR3 0xFFFDFC
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#define EDMDR3H 0xFFFDFC
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#define EDMDR3L 0xFFFDFD
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#define EDACR3 0xFFFDFE
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#define IPRA 0xFFFE00
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#define IPRB 0xFFFE02
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#define IPRC 0xFFFE04
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#define IPRD 0xFFFE06
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#define IPRE 0xFFFE08
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#define IPRF 0xFFFE0A
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#define IPRG 0xFFFE0C
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#define IPRH 0xFFFE0E
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#define IPRI 0xFFFE10
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#define IPRJ 0xFFFE12
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#define IPRK 0xFFFE14
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#define ITSR 0xFFFE16
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#define SSIER 0xFFFE18
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#define ISCRH 0xFFFE1A
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#define ISCRL 0xFFFE1C
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#define INTCR 0xFFFF31
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#define IER 0xFFFF32
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#define IERH 0xFFFF32
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#define IERL 0xFFFF33
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#define ISR 0xFFFF34
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#define ISRH 0xFFFF34
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#define ISRL 0xFFFF35
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#define P1DDR 0xFFFE20
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#define P2DDR 0xFFFE21
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#define P3DDR 0xFFFE22
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#define P4DDR 0xFFFE23
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#define P5DDR 0xFFFE24
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#define P6DDR 0xFFFE25
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#define P7DDR 0xFFFE26
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#define P8DDR 0xFFFE27
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#define P9DDR 0xFFFE28
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#define PADDR 0xFFFE29
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#define PBDDR 0xFFFE2A
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#define PCDDR 0xFFFE2B
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#define PDDDR 0xFFFE2C
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#define PEDDR 0xFFFE2D
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#define PFDDR 0xFFFE2E
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#define PGDDR 0xFFFE2F
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#define PHDDR 0xFFFF74
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#define PFCR0 0xFFFE32
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#define PFCR1 0xFFFE33
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#define PFCR2 0xFFFE34
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#define PAPCR 0xFFFE36
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#define PBPCR 0xFFFE37
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#define PCPCR 0xFFFE38
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#define PDPCR 0xFFFE39
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#define PEPCR 0xFFFE3A
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#define P3ODR 0xFFFE3C
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#define PAODR 0xFFFE3D
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#define P1DR 0xFFFF60
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#define P2DR 0xFFFF61
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#define P3DR 0xFFFF62
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#define P4DR 0xFFFF63
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#define P5DR 0xFFFF64
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#define P6DR 0xFFFF65
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#define P7DR 0xFFFF66
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#define P8DR 0xFFFF67
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#define P9DR 0xFFFF68
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#define PADR 0xFFFF69
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#define PBDR 0xFFFF6A
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#define PCDR 0xFFFF6B
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#define PDDR 0xFFFF6C
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#define PEDR 0xFFFF6D
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#define PFDR 0xFFFF6E
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#define PGDR 0xFFFF6F
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#define PHDR 0xFFFF72
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#define PORT1 0xFFFF50
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#define PORT2 0xFFFF51
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#define PORT3 0xFFFF52
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#define PORT4 0xFFFF53
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#define PORT5 0xFFFF54
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#define PORT6 0xFFFF55
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#define PORT7 0xFFFF56
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#define PORT8 0xFFFF57
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#define PORT9 0xFFFF58
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#define PORTA 0xFFFF59
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#define PORTB 0xFFFF5A
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#define PORTC 0xFFFF5B
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#define PORTD 0xFFFF5C
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#define PORTE 0xFFFF5D
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#define PORTF 0xFFFF5E
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#define PORTG 0xFFFF5F
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#define PORTH 0xFFFF70
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#define PCR 0xFFFF46
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#define PMR 0xFFFF47
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#define NDERH 0xFFFF48
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#define NDERL 0xFFFF49
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#define PODRH 0xFFFF4A
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#define PODRL 0xFFFF4B
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#define NDRH1 0xFFFF4C
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#define NDRL1 0xFFFF4D
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#define NDRH2 0xFFFF4E
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#define NDRL2 0xFFFF4F
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#define SMR0 0xFFFF78
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#define BRR0 0xFFFF79
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#define SCR0 0xFFFF7A
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#define TDR0 0xFFFF7B
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#define SSR0 0xFFFF7C
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#define RDR0 0xFFFF7D
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#define SCMR0 0xFFFF7E
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#define SMR1 0xFFFF80
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#define BRR1 0xFFFF81
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#define SCR1 0xFFFF82
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#define TDR1 0xFFFF83
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#define SSR1 0xFFFF84
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#define RDR1 0xFFFF85
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#define SCMR1 0xFFFF86
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#define SMR2 0xFFFF88
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#define BRR2 0xFFFF89
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#define SCR2 0xFFFF8A
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#define TDR2 0xFFFF8B
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#define SSR2 0xFFFF8C
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#define RDR2 0xFFFF8D
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#define SCMR2 0xFFFF8E
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#define IRCR0 0xFFFE1E
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#define SEMR 0xFFFDA8
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#define MDCR 0xFFFF3E
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#define SYSCR 0xFFFF3D
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#define MSTPCRH 0xFFFF40
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#define MSTPCRL 0xFFFF41
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#define FLMCR1 0xFFFFC8
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#define FLMCR2 0xFFFFC9
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#define EBR1 0xFFFFCA
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#define EBR2 0xFFFFCB
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#define CTGARC_RAMCR 0xFFFECE
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#define SBYCR 0xFFFF3A
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#define SCKCR 0xFFFF3B
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#define PLLCR 0xFFFF45
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#define TSTR 0xFFFFC0
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#define TSNC 0XFFFFC1
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#define TCR0 0xFFFFD0
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#define TMDR0 0xFFFFD1
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#define TIORH0 0xFFFFD2
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#define TIORL0 0xFFFFD3
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#define TIER0 0xFFFFD4
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#define TSR0 0xFFFFD5
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#define TCNT0 0xFFFFD6
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#define GRA0 0xFFFFD8
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#define GRB0 0xFFFFDA
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#define GRC0 0xFFFFDC
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#define GRD0 0xFFFFDE
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#define TCR1 0xFFFFE0
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#define TMDR1 0xFFFFE1
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#define TIORH1 0xFFFFE2
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#define TIORL1 0xFFFFE3
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#define TIER1 0xFFFFE4
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#define TSR1 0xFFFFE5
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#define TCNT1 0xFFFFE6
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#define GRA1 0xFFFFE8
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#define GRB1 0xFFFFEA
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#define TCR2 0xFFFFF0
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#define TMDR2 0xFFFFF1
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#define TIORH2 0xFFFFF2
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#define TIORL2 0xFFFFF3
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#define TIER2 0xFFFFF4
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#define TSR2 0xFFFFF5
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#define TCNT2 0xFFFFF6
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#define GRA2 0xFFFFF8
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#define GRB2 0xFFFFFA
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#define TCR3 0xFFFE80
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#define TMDR3 0xFFFE81
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#define TIORH3 0xFFFE82
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#define TIORL3 0xFFFE83
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#define TIER3 0xFFFE84
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#define TSR3 0xFFFE85
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#define TCNT3 0xFFFE86
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#define GRA3 0xFFFE88
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#define GRB3 0xFFFE8A
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#define GRC3 0xFFFE8C
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#define GRD3 0xFFFE8E
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#define TCR4 0xFFFE90
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#define TMDR4 0xFFFE91
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#define TIORH4 0xFFFE92
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#define TIORL4 0xFFFE93
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#define TIER4 0xFFFE94
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#define TSR4 0xFFFE95
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#define TCNT4 0xFFFE96
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#define GRA4 0xFFFE98
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#define GRB4 0xFFFE9A
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#define TCR5 0xFFFEA0
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#define TMDR5 0xFFFEA1
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#define TIORH5 0xFFFEA2
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#define TIORL5 0xFFFEA3
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#define TIER5 0xFFFEA4
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#define TSR5 0xFFFEA5
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#define TCNT5 0xFFFEA6
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#define GRA5 0xFFFEA8
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#define GRB5 0xFFFEAA
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#define _8TCR0 0xFFFFB0
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#define _8TCR1 0xFFFFB1
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#define _8TCSR0 0xFFFFB2
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#define _8TCSR1 0xFFFFB3
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#define _8TCORA0 0xFFFFB4
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#define _8TCORA1 0xFFFFB5
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#define _8TCORB0 0xFFFFB6
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#define _8TCORB1 0xFFFFB7
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#define _8TCNT0 0xFFFFB8
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#define _8TCNT1 0xFFFFB9
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#define TCSR 0xFFFFBC
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#define TCNT 0xFFFFBD
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#define RSTCSRW 0xFFFFBE
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#define RSTCSRR 0xFFFFBF
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#endif /* __KERNEL__ */
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#endif /* __REGS_H8S267x__ */
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