mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 00:25:02 +07:00
50a5065f44
According to internal documents I found for CMP PCHs the PCI ID 0xA3C1
belongs to a CMP-V chipset. Based on the same docs the programming of
the PCH is compatible with that of KBP. Fix up my previous wrong
assumption accordingly using the SPT programming which in turn is the
basis for KBP.
The original bug reporter verified that this is the correct PCH
identification (the only way we'll program valid DDC pin-pair values to
the GMBUS register) and the Windows team uses the same identification
(that is using the KBP programming model for this PCH).
I filed the necessary Bspec update requests (BSpec/33734).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112051
Fixes: 37c92dc303 ("drm/i915: Add new CNL PCH ID seen on a CML platform")
Reported-and-tested-by: Cyrus <cyrus.lien@canonical.com>
Cc: Cyrus <cyrus.lien@canonical.com>
Cc: Timo Aaltonen <tjaalton@ubuntu.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191112104608.24587-1-imre.deak@intel.com
80 lines
3.2 KiB
C
80 lines
3.2 KiB
C
/* SPDX-License-Identifier: MIT */
|
|
/*
|
|
* Copyright 2019 Intel Corporation.
|
|
*/
|
|
|
|
#ifndef __INTEL_PCH__
|
|
#define __INTEL_PCH__
|
|
|
|
struct drm_i915_private;
|
|
|
|
/*
|
|
* Sorted by south display engine compatibility.
|
|
* If the new PCH comes with a south display engine that is not
|
|
* inherited from the latest item, please do not add it to the
|
|
* end. Instead, add it right after its "parent" PCH.
|
|
*/
|
|
enum intel_pch {
|
|
PCH_NOP = -1, /* PCH without south display */
|
|
PCH_NONE = 0, /* No PCH present */
|
|
PCH_IBX, /* Ibexpeak PCH */
|
|
PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
|
|
PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
|
|
PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
|
|
PCH_CNP, /* Cannon/Comet Lake PCH */
|
|
PCH_ICP, /* Ice Lake PCH */
|
|
PCH_JSP, /* Jasper Lake PCH */
|
|
PCH_MCC, /* Mule Creek Canyon PCH */
|
|
PCH_TGP, /* Tiger Lake PCH */
|
|
};
|
|
|
|
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
|
|
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
|
|
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
|
|
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
|
|
#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
|
|
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
|
|
#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
|
|
#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
|
|
#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
|
|
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
|
|
#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
|
|
#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
|
|
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
|
|
#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
|
|
#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680
|
|
#define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA380
|
|
#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
|
|
#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
|
|
#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
|
|
#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380
|
|
#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
|
|
#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
|
|
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
|
|
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
|
|
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
|
|
|
|
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
|
|
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
|
|
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
|
|
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
|
|
#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
|
|
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
|
|
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
|
|
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
|
|
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
|
|
#define HAS_PCH_LPT_LP(dev_priv) \
|
|
(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
|
|
INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
|
|
#define HAS_PCH_LPT_H(dev_priv) \
|
|
(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
|
|
INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
|
|
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
|
|
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
|
|
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
|
|
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
|
|
|
|
void intel_detect_pch(struct drm_i915_private *dev_priv);
|
|
|
|
#endif /* __INTEL_PCH__ */
|