mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 19:57:38 +07:00
2e554390ab
BG2CD SoC uses r3p0 Cortex-A9 MPCore single-CPU cluster. Autoselect pertinent errata, the SCU and the global timer, and allow use of the local timer on uniprocessor kernels. PL310 L2 cache controller has revision r3p2; no errata to select. Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
42 lines
866 B
Plaintext
42 lines
866 B
Plaintext
menuconfig ARCH_BERLIN
|
|
bool "Marvell Berlin SoCs"
|
|
depends on ARCH_MULTI_V7
|
|
select ARCH_HAS_RESET_CONTROLLER
|
|
select ARM_GIC
|
|
select DW_APB_ICTL
|
|
select DW_APB_TIMER_OF
|
|
select GENERIC_IRQ_CHIP
|
|
select GPIOLIB
|
|
select MFD_SYSCON
|
|
select PINCTRL
|
|
|
|
if ARCH_BERLIN
|
|
|
|
config MACH_BERLIN_BG2
|
|
bool "Marvell Armada 1500 (BG2)"
|
|
select CACHE_L2X0
|
|
select CPU_PJ4B
|
|
select HAVE_ARM_SCU if SMP
|
|
select HAVE_ARM_TWD if SMP
|
|
select HAVE_SMP
|
|
select PINCTRL_BERLIN_BG2
|
|
|
|
config MACH_BERLIN_BG2CD
|
|
bool "Marvell Armada 1500-mini (BG2CD)"
|
|
select ARM_ERRATA_754322
|
|
select ARM_ERRATA_775420
|
|
select ARM_GLOBAL_TIMER
|
|
select CACHE_L2X0
|
|
select HAVE_ARM_SCU
|
|
select HAVE_ARM_TWD
|
|
select PINCTRL_BERLIN_BG2CD
|
|
|
|
config MACH_BERLIN_BG2Q
|
|
bool "Marvell Armada 1500 Pro (BG2-Q)"
|
|
select CACHE_L2X0
|
|
select HAVE_ARM_SCU if SMP
|
|
select HAVE_ARM_TWD if SMP
|
|
select PINCTRL_BERLIN_BG2Q
|
|
|
|
endif
|