linux_dsm_epyc7002/arch/mips/alchemy/devboards
Thomas Gleixner e0288a0a7b MIPS: alchemy: Remove pointless irqdisable/enable
bcsr_csc_handler() is a cascading interrupt handler. It has a
disable_irq_nosync()/enable_irq() pair around the generic_handle_irq()
call. The value of this disable/enable is zero because its a complete
noop:

disable_irq_nosync() merily increments the disable count without
actually masking the interrupt. enable_irq() soleley decrements the
disable count without touching the interrupt chip. The interrupt
cannot arrive again because the complete call chain runs with
interrupts disabled.

Remove it.

[ralf@linux-mips.org: Fold in followup fix from Thomas Gleixner.]

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Cc: LKML <linux-kernel@vger.kernel.org>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Patchwork: https://patchwork.linux-mips.org/patch/10702/
Patchwork: https://patchwork.linux-mips.org/patch/10708/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-08-26 15:23:30 +02:00
..
bcsr.c MIPS: alchemy: Remove pointless irqdisable/enable 2015-08-26 15:23:30 +02:00
db1xxx.c MIPS: Alchemy: Unify Devboard support. 2014-03-26 23:09:21 +01:00
db1000.c MIPS: Alchemy: au1100fb: use clk framework 2014-07-30 14:10:39 +02:00
db1200.c MIPS: Alchemy: Fix db1200 PSC clock enablement 2014-08-19 13:30:47 +02:00
db1300.c MIPS: Alchemy: DB1300: Add touch penirq support 2014-09-22 13:35:47 +02:00
db1550.c MIPS: Alchemy: DB1xxx: Explicitly set 50MHz clock for I2C/SPI units. 2014-09-22 13:35:47 +02:00
Makefile MIPS: Alchemy: Unify Devboard support. 2014-03-26 23:09:21 +01:00
platform.c MIPS: Alchemy: devboards: sit and spin after poweroff 2014-09-22 13:35:46 +02:00
platform.h MIPS: Alchemy: use 36bit addresses for PCMCIA resources. 2010-02-27 12:53:43 +01:00
pm.c MIPS: Alchemy: introduce helpers to access SYS register block. 2014-07-30 13:53:28 +02:00