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d8f7f3228a
The si_code of 0 (aka SI_USER) has fields si_pid and si_uid not
si_addr so it so only by luck would the appropriate fields by copied
to userspace by copy_siginfo_to_user.
This is just broken and wrong.
Make it obvious what is happening by moving the si_code from a
parameter of the one call to ucf64_raise_sigfpe to a constant value
that info.si_code gets set to.
Explicitly set the si_code to FPE_FLTUNK the newly reserved floating
point si_code for an unknown floating point exception.
It looks like there is a fair chance that this is a code path that has
never been used in real life on unicore32. The bad si_code and the
print statement that calls it an unhandled exception. So I really
don't expect anyone will mind if this just gets fixed.
In similar situations on more popular architectures the conclusion was
just fix it.
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: Arnd Bergmann <arnd@arndb.de>
Fixes: d9bc15794d ("unicore32 additional architecture files: float point handling")
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
127 lines
2.9 KiB
C
127 lines
2.9 KiB
C
/*
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* linux/arch/unicore32/kernel/fpu-ucf64.c
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/signal.h>
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#include <linux/sched/signal.h>
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#include <linux/init.h>
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#include <asm/fpu-ucf64.h>
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/*
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* A special flag to tell the normalisation code not to normalise.
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*/
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#define F64_NAN_FLAG 0x100
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/*
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* A bit pattern used to indicate the initial (unset) value of the
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* exception mask, in case nothing handles an instruction. This
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* doesn't include the NAN flag, which get masked out before
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* we check for an error.
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*/
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#define F64_EXCEPTION_ERROR ((u32)-1 & ~F64_NAN_FLAG)
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/*
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* Since we aren't building with -mfpu=f64, we need to code
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* these instructions using their MRC/MCR equivalents.
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*/
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#define f64reg(_f64_) #_f64_
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#define cff(_f64_) ({ \
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u32 __v; \
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asm("cff %0, " f64reg(_f64_) "@ fmrx %0, " #_f64_ \
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: "=r" (__v) : : "cc"); \
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__v; \
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})
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#define ctf(_f64_, _var_) \
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asm("ctf %0, " f64reg(_f64_) "@ fmxr " #_f64_ ", %0" \
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: : "r" (_var_) : "cc")
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/*
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* Raise a SIGFPE for the current process.
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* sicode describes the signal being raised.
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*/
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void ucf64_raise_sigfpe(struct pt_regs *regs)
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{
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siginfo_t info;
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clear_siginfo(&info);
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info.si_signo = SIGFPE;
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info.si_code = FPE_FLTUNK;
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info.si_addr = (void __user *)(instruction_pointer(regs) - 4);
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/*
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* This is the same as NWFPE, because it's not clear what
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* this is used for
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*/
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current->thread.error_code = 0;
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current->thread.trap_no = 6;
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send_sig_info(SIGFPE, &info, current);
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}
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/*
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* Handle exceptions of UniCore-F64.
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*/
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void ucf64_exchandler(u32 inst, u32 fpexc, struct pt_regs *regs)
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{
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u32 tmp = fpexc;
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u32 exc = F64_EXCEPTION_ERROR & fpexc;
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pr_debug("UniCore-F64: instruction %08x fpscr %08x\n",
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inst, fpexc);
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if (exc & FPSCR_CMPINSTR_BIT) {
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if (exc & FPSCR_CON)
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tmp |= FPSCR_CON;
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else
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tmp &= ~(FPSCR_CON);
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exc &= ~(FPSCR_CMPINSTR_BIT | FPSCR_CON);
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} else {
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pr_debug("UniCore-F64 Error: unhandled exceptions\n");
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pr_debug("UniCore-F64 FPSCR 0x%08x INST 0x%08x\n",
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cff(FPSCR), inst);
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ucf64_raise_sigfpe(regs);
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return;
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}
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/*
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* Update the FPSCR with the additional exception flags.
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* Comparison instructions always return at least one of
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* these flags set.
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*/
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tmp &= ~(FPSCR_TRAP | FPSCR_IOS | FPSCR_OFS | FPSCR_UFS |
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FPSCR_IXS | FPSCR_HIS | FPSCR_IOC | FPSCR_OFC |
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FPSCR_UFC | FPSCR_IXC | FPSCR_HIC);
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tmp |= exc;
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ctf(FPSCR, tmp);
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}
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/*
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* F64 support code initialisation.
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*/
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static int __init ucf64_init(void)
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{
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ctf(FPSCR, 0x0); /* FPSCR_UFE | FPSCR_NDE perhaps better */
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printk(KERN_INFO "Enable UniCore-F64 support.\n");
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return 0;
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}
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late_initcall(ucf64_init);
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