mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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77d7676a92
In preparation for allowing to build QE support for architectures other than PPC, replace the ppc-specific io accessors by the qe_io* macros. Done via $ spatch --sp-file io.cocci --in-place drivers/soc/fsl/qe/ where io.cocci is @@ expression addr, val; @@ - out_be32(addr, val) + qe_iowrite32be(val, addr) @@ expression addr; @@ - in_be32(addr) + qe_ioread32be(addr) @@ expression addr, val; @@ - out_be16(addr, val) + qe_iowrite16be(val, addr) @@ expression addr; @@ - in_be16(addr) + qe_ioread16be(addr) @@ expression addr, val; @@ - out_8(addr, val) + qe_iowrite8(val, addr) @@ expression addr; @@ - in_8(addr) + qe_ioread8(addr) @@ expression addr, clr, set; @@ - clrsetbits_be32(addr, clr, set) + qe_clrsetbits_be32(addr, clr, set) @@ expression addr, clr, set; @@ - clrsetbits_be16(addr, clr, set) + qe_clrsetbits_be16(addr, clr, set) @@ expression addr, clr, set; @@ - clrsetbits_8(addr, clr, set) + qe_clrsetbits_8(addr, clr, set) @@ expression addr, set; @@ - setbits32(addr, set) + qe_setbits_be32(addr, set) @@ expression addr, set; @@ - setbits16(addr, set) + qe_setbits_be16(addr, set) @@ expression addr, set; @@ - setbits8(addr, set) + qe_setbits_8(addr, set) @@ expression addr, clr; @@ - clrbits32(addr, clr) + qe_clrbits_be32(addr, clr) @@ expression addr, clr; @@ - clrbits16(addr, clr) + qe_clrbits_be16(addr, clr) @@ expression addr, clr; @@ - clrbits8(addr, clr) + qe_clrbits_8(addr, clr) Reviewed-by: Timur Tabi <timur@kernel.org> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Li Yang <leoyang.li@nxp.com>
53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* QE USB routines
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*
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* Copyright 2006 Freescale Semiconductor, Inc.
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* Shlomi Gridish <gridish@freescale.com>
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* Jerry Huang <Chang-Ming.Huang@freescale.com>
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* Copyright (c) MontaVista Software, Inc. 2008.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/io.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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int qe_usb_clock_set(enum qe_clock clk, int rate)
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{
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struct qe_mux __iomem *mux = &qe_immr->qmx;
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unsigned long flags;
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u32 val;
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switch (clk) {
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case QE_CLK3: val = QE_CMXGCR_USBCS_CLK3; break;
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case QE_CLK5: val = QE_CMXGCR_USBCS_CLK5; break;
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case QE_CLK7: val = QE_CMXGCR_USBCS_CLK7; break;
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case QE_CLK9: val = QE_CMXGCR_USBCS_CLK9; break;
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case QE_CLK13: val = QE_CMXGCR_USBCS_CLK13; break;
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case QE_CLK17: val = QE_CMXGCR_USBCS_CLK17; break;
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case QE_CLK19: val = QE_CMXGCR_USBCS_CLK19; break;
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case QE_CLK21: val = QE_CMXGCR_USBCS_CLK21; break;
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case QE_BRG9: val = QE_CMXGCR_USBCS_BRG9; break;
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case QE_BRG10: val = QE_CMXGCR_USBCS_BRG10; break;
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default:
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pr_err("%s: requested unknown clock %d\n", __func__, clk);
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return -EINVAL;
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}
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if (qe_clock_is_brg(clk))
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qe_setbrg(clk, rate, 1);
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spin_lock_irqsave(&cmxgcr_lock, flags);
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qe_clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
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spin_unlock_irqrestore(&cmxgcr_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(qe_usb_clock_set);
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