mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 13:32:50 +07:00
1641567920
CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents, it has internal clock divider and a clock skipper. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is selected as a parent for CCLK. This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock selection into the clock driver. Note that technically this patch could be squashed into clk-super.c, but it is cleaner to have a separate source file. Also note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
32 lines
1.1 KiB
Makefile
32 lines
1.1 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
|
|
obj-y += clk.o
|
|
obj-y += clk-audio-sync.o
|
|
obj-y += clk-dfll.o
|
|
obj-y += clk-divider.o
|
|
obj-y += clk-periph.o
|
|
obj-y += clk-periph-fixed.o
|
|
obj-y += clk-periph-gate.o
|
|
obj-y += clk-pll.o
|
|
obj-y += clk-pll-out.o
|
|
obj-y += clk-sdmmc-mux.o
|
|
obj-y += clk-super.o
|
|
obj-y += clk-tegra-audio.o
|
|
obj-y += clk-tegra-periph.o
|
|
obj-y += clk-tegra-fixed.o
|
|
obj-y += clk-tegra-super-cclk.o
|
|
obj-y += clk-tegra-super-gen4.o
|
|
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
|
|
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20-emc.o
|
|
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
|
|
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra20-emc.o
|
|
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
|
|
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
|
|
obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o
|
|
obj-$(CONFIG_TEGRA124_EMC) += clk-tegra124-emc.o
|
|
obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
|
|
obj-y += cvb.o
|
|
obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
|
|
obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210-emc.o
|
|
obj-$(CONFIG_CLK_TEGRA_BPMP) += clk-bpmp.o
|
|
obj-y += clk-utils.o
|