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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0baada2742
Ensure that if the RTC IRQ is not selected for wake in the base configuration, then the PWRCFG has the same value set in it. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
215 lines
5.5 KiB
C
215 lines
5.5 KiB
C
/* linux/arch/arm/mach-s3c2412/irq.c
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/sysdev.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/regs-irq.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-power.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#include <asm/plat-s3c24xx/irq.h>
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#include <asm/plat-s3c24xx/pm.h>
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#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
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#define INTMSK_SUB(start, end) (INTMSK(start, end) << ((start - S3C2410_IRQSUB(0))))
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/* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
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* having them turn up in both the INT* and the EINT* registers. Whilst
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* both show the status, they both now need to be acked when the IRQs
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* go off.
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*/
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static void
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s3c2412_irq_mask(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask | bitval, S3C2410_INTMSK);
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask | bitval, S3C2412_EINTMASK);
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}
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static inline void
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s3c2412_irq_ack(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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__raw_writel(bitval, S3C2412_EINTPEND);
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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}
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static inline void
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s3c2412_irq_maskack(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask|bitval, S3C2410_INTMSK);
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask | bitval, S3C2412_EINTMASK);
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__raw_writel(bitval, S3C2412_EINTPEND);
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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}
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static void
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s3c2412_irq_unmask(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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unsigned long mask;
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mask = __raw_readl(S3C2412_EINTMASK);
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__raw_writel(mask & ~bitval, S3C2412_EINTMASK);
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask & ~bitval, S3C2410_INTMSK);
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}
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static struct irq_chip s3c2412_irq_eint0t4 = {
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.ack = s3c2412_irq_ack,
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.mask = s3c2412_irq_mask,
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.unmask = s3c2412_irq_unmask,
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.set_wake = s3c_irq_wake,
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.set_type = s3c_irqext_type,
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};
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#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0)))
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/* CF and SDI sub interrupts */
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static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int subsrc, submsk;
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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if (subsrc & INTBIT(IRQ_S3C2412_SDI))
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desc_handle_irq(IRQ_S3C2412_SDI, irq_desc + IRQ_S3C2412_SDI);
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if (subsrc & INTBIT(IRQ_S3C2412_CF))
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desc_handle_irq(IRQ_S3C2412_CF, irq_desc + IRQ_S3C2412_CF);
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}
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#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
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#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
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static void s3c2412_irq_cfsdi_mask(unsigned int irqno)
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{
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s3c_irqsub_mask(irqno, INTMSK_CFSDI, SUBMSK_CFSDI);
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}
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static void s3c2412_irq_cfsdi_unmask(unsigned int irqno)
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{
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s3c_irqsub_unmask(irqno, INTMSK_CFSDI);
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}
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static void s3c2412_irq_cfsdi_ack(unsigned int irqno)
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{
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s3c_irqsub_maskack(irqno, INTMSK_CFSDI, SUBMSK_CFSDI);
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}
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static struct irq_chip s3c2412_irq_cfsdi = {
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.name = "s3c2412-cfsdi",
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.ack = s3c2412_irq_cfsdi_ack,
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.mask = s3c2412_irq_cfsdi_mask,
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.unmask = s3c2412_irq_cfsdi_unmask,
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};
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static int s3c2412_irq_rtc_wake(unsigned int irqno, unsigned int state)
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{
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unsigned long pwrcfg;
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pwrcfg = __raw_readl(S3C2412_PWRCFG);
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if (state)
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pwrcfg &= ~S3C2412_PWRCFG_RTC_MASKIRQ;
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else
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pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
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__raw_writel(pwrcfg, S3C2412_PWRCFG);
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return s3c_irq_chip.set_wake(irqno, state);
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}
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static struct irq_chip s3c2412_irq_rtc_chip;
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static int s3c2412_irq_add(struct sys_device *sysdev)
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{
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unsigned int irqno;
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for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
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set_irq_chip(irqno, &s3c2412_irq_eint0t4);
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set_irq_handler(irqno, handle_edge_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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/* add demux support for CF/SDI */
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set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
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for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
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set_irq_chip(irqno, &s3c2412_irq_cfsdi);
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set_irq_handler(irqno, handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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/* change RTC IRQ's set wake method */
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s3c2412_irq_rtc_chip = s3c_irq_chip;
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s3c2412_irq_rtc_chip.set_wake = s3c2412_irq_rtc_wake;
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set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
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return 0;
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}
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static struct sysdev_driver s3c2412_irq_driver = {
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.add = s3c2412_irq_add,
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.suspend = s3c24xx_irq_suspend,
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.resume = s3c24xx_irq_resume,
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};
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static int s3c2412_irq_init(void)
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{
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return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver);
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}
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arch_initcall(s3c2412_irq_init);
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