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2e1a7b014f
Currently, DPLLs are hiding the gory details of switching parent within set_rate, which confuses the common clock code and is wrong. Fixed by applying the new determine_rate() and set_rate_and_parent() functionality to any clock-ops previously using the broken approach. This patch also removes the broken legacy code. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> |
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.. | ||
apll.c | ||
autoidle.c | ||
clk-2xxx.c | ||
clk-3xxx.c | ||
clk-7xx.c | ||
clk-33xx.c | ||
clk-43xx.c | ||
clk-44xx.c | ||
clk-54xx.c | ||
clk-dra7-atl.c | ||
clk.c | ||
clockdomain.c | ||
composite.c | ||
divider.c | ||
dpll.c | ||
fixed-factor.c | ||
gate.c | ||
interface.c | ||
Makefile | ||
mux.c |