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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c4df4bc155
Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Acked-by: John Linn <john.linn@xilinx.com> Acked-by: John Williams <john.williams@petalogix.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
459 lines
12 KiB
ArmAsm
459 lines
12 KiB
ArmAsm
/*
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* Exception handling for Microblaze
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*
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* Rewriten interrupt handling
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*
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* Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008-2009 PetaLogix
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*
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* uClinux customisation (C) 2005 John Williams
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*
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* MMU code derived from arch/ppc/kernel/head_4xx.S:
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* Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
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* Initial PowerPC version.
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Rewritten for PReP
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* Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
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* Low-level exception handers, MMU support, and rewrite.
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* Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
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* PowerPC 8xx modifications.
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* Copyright (C) 1998-1999 TiVo, Inc.
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* PowerPC 403GCX modifications.
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* Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
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* PowerPC 403GCX/405GP modifications.
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* Copyright 2000 MontaVista Software Inc.
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* PPC405 modifications
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* PowerPC 403GCX/405GP modifications.
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* Author: MontaVista Software, Inc.
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* frank_rowand@mvista.com or source@mvista.com
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* debbie_chu@mvista.com
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*
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* Original code
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* Copyright (C) 2004 Xilinx, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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/*
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* Here are the handlers which don't require enabling translation
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* and calling other kernel code thus we can keep their design very simple
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* and do all processing in real mode. All what they need is a valid current
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* (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
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* This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
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* these registers are saved/restored
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* The handlers which require translation are in entry.S --KAA
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*
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* Microblaze HW Exception Handler
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* - Non self-modifying exception handler for the following exception conditions
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* - Unalignment
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* - Instruction bus error
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* - Data bus error
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* - Illegal instruction opcode
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* - Divide-by-zero
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*
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* Note we disable interrupts during exception handling, otherwise we will
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* possibly get multiple re-entrancy if interrupt handles themselves cause
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* exceptions. JW
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*/
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#include <asm/exceptions.h>
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#include <asm/unistd.h>
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#include <asm/page.h>
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#include <asm/entry.h>
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#include <asm/current.h>
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#include <linux/linkage.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/asm-offsets.h>
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/* Helpful Macros */
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#define EX_HANDLER_STACK_SIZ (4*19)
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#define NUM_TO_REG(num) r ## num
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#define LWREG_NOP \
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bri ex_handler_unhandled; \
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nop;
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#define SWREG_NOP \
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bri ex_handler_unhandled; \
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nop;
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/* FIXME this is weird - for noMMU kernel is not possible to use brid
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* instruction which can shorten executed time
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*/
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/* r3 is the source */
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#define R3_TO_LWREG_V(regnum) \
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swi r3, r1, 4 * regnum; \
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bri ex_handler_done;
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/* r3 is the source */
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#define R3_TO_LWREG(regnum) \
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or NUM_TO_REG (regnum), r0, r3; \
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bri ex_handler_done;
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/* r3 is the target */
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#define SWREG_TO_R3_V(regnum) \
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lwi r3, r1, 4 * regnum; \
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bri ex_sw_tail;
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/* r3 is the target */
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#define SWREG_TO_R3(regnum) \
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or r3, r0, NUM_TO_REG (regnum); \
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bri ex_sw_tail;
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.extern other_exception_handler /* Defined in exception.c */
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/*
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* hw_exception_handler - Handler for exceptions
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*
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* Exception handler notes:
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* - Handles all exceptions
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* - Does not handle unaligned exceptions during load into r17, r1, r0.
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* - Does not handle unaligned exceptions during store from r17 (cannot be
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* done) and r1 (slows down common case)
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*
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* Relevant register structures
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*
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* EAR - |----|----|----|----|----|----|----|----|
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* - < ## 32 bit faulting address ## >
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*
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* ESR - |----|----|----|----|----| - | - |-----|-----|
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* - W S REG EXC
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*
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*
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* STACK FRAME STRUCTURE (for NO_MMU)
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* ---------------------------------
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*
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* +-------------+ + 0
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* | MSR |
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* +-------------+ + 4
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* | r1 |
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* | . |
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* | . |
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* | . |
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* | . |
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* | r18 |
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* +-------------+ + 76
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* | . |
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* | . |
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*
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* NO_MMU kernel use the same r0_ram pointed space - look to vmlinux.lds.S
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* which is used for storing register values - old style was, that value were
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* stored in stack but in case of failure you lost information about register.
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* Currently you can see register value in memory in specific place.
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* In compare to with previous solution the speed should be the same.
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*
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* MMU exception handler has different handling compare to no MMU kernel.
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* Exception handler use jump table for directing of what happen. For MMU kernel
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* is this approach better because MMU relate exception are handled by asm code
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* in this file. In compare to with MMU expect of unaligned exception
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* is everything handled by C code.
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*/
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/*
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* every of these handlers is entered having R3/4/5/6/11/current saved on stack
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* and clobbered so care should be taken to restore them if someone is going to
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* return from exception
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*/
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/* wrappers to restore state before coming to entry.S */
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.global _hw_exception_handler
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.section .text
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.align 4
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.ent _hw_exception_handler
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_hw_exception_handler:
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addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
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swi r3, r1, PT_R3
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swi r4, r1, PT_R4
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swi r5, r1, PT_R5
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swi r6, r1, PT_R6
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mfs r5, rmsr;
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nop
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swi r5, r1, 0;
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mfs r4, rbtr /* Save BTR before jumping to handler */
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nop
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mfs r3, resr
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nop
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andi r5, r3, 0x1000; /* Check ESR[DS] */
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beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */
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mfs r17, rbtr; /* ESR[DS] set - return address in BTR */
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nop
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not_in_delay_slot:
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swi r17, r1, PT_R17
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andi r5, r3, 0x1F; /* Extract ESR[EXC] */
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/* Exceptions enabled here. This will allow nested exceptions */
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mfs r6, rmsr;
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nop
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swi r6, r1, 0; /* RMSR_OFFSET */
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ori r6, r6, 0x100; /* Turn ON the EE bit */
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andi r6, r6, ~2; /* Disable interrupts */
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mts rmsr, r6;
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nop
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xori r6, r5, 1; /* 00001 = Unaligned Exception */
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/* Jump to unalignment exception handler */
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beqi r6, handle_unaligned_ex;
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handle_other_ex: /* Handle Other exceptions here */
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/* Save other volatiles before we make procedure calls below */
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swi r7, r1, PT_R7
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swi r8, r1, PT_R8
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swi r9, r1, PT_R9
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swi r10, r1, PT_R10
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swi r11, r1, PT_R11
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swi r12, r1, PT_R12
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swi r14, r1, PT_R14
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swi r15, r1, PT_R15
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swi r18, r1, PT_R18
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or r5, r1, r0
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andi r6, r3, 0x1F; /* Load ESR[EC] */
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lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
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swi r7, r1, PT_MODE
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mfs r7, rfsr
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nop
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addk r8, r17, r0; /* Load exception address */
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bralid r15, full_exception; /* Branch to the handler */
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nop;
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/*
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* Trigger execution of the signal handler by enabling
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* interrupts and calling an invalid syscall.
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*/
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mfs r5, rmsr;
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nop
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ori r5, r5, 2;
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mts rmsr, r5; /* enable interrupt */
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nop
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addi r12, r0, __NR_syscalls;
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brki r14, 0x08;
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mfs r5, rmsr; /* disable interrupt */
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nop
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andi r5, r5, ~2;
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mts rmsr, r5;
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nop
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lwi r7, r1, PT_R7
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lwi r8, r1, PT_R8
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lwi r9, r1, PT_R9
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lwi r10, r1, PT_R10
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lwi r11, r1, PT_R11
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lwi r12, r1, PT_R12
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lwi r14, r1, PT_R14
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lwi r15, r1, PT_R15
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lwi r18, r1, PT_R18
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bri ex_handler_done; /* Complete exception handling */
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/* 0x01 - Unaligned data access exception
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* This occurs when a word access is not aligned on a word boundary,
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* or when a 16-bit access is not aligned on a 16-bit boundary.
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* This handler perform the access, and returns, except for MMU when
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* the unaligned address is last on a 4k page or the physical address is
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* not found in the page table, in which case unaligned_data_trap is called.
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*/
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handle_unaligned_ex:
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/* Working registers already saved: R3, R4, R5, R6
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* R3 = ESR
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* R4 = BTR
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*/
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mfs r4, rear;
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nop
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andi r6, r3, 0x3E0; /* Mask and extract the register operand */
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srl r6, r6; /* r6 >> 5 */
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srl r6, r6;
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srl r6, r6;
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srl r6, r6;
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srl r6, r6;
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/* Store the register operand in a temporary location */
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sbi r6, r0, TOPHYS(ex_reg_op);
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andi r6, r3, 0x400; /* Extract ESR[S] */
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bnei r6, ex_sw;
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ex_lw:
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andi r6, r3, 0x800; /* Extract ESR[W] */
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beqi r6, ex_lhw;
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lbui r5, r4, 0; /* Exception address in r4 */
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/* Load a word, byte-by-byte from destination address
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and save it in tmp space */
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
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lbui r5, r4, 1;
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
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lbui r5, r4, 2;
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);
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lbui r5, r4, 3;
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_3);
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/* Get the destination register value into r3 */
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lwi r3, r0, TOPHYS(ex_tmp_data_loc_0);
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bri ex_lw_tail;
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ex_lhw:
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lbui r5, r4, 0; /* Exception address in r4 */
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/* Load a half-word, byte-by-byte from destination
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address and save it in tmp space */
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_0);
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lbui r5, r4, 1;
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sbi r5, r0, TOPHYS(ex_tmp_data_loc_1);
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/* Get the destination register value into r3 */
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lhui r3, r0, TOPHYS(ex_tmp_data_loc_0);
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ex_lw_tail:
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/* Get the destination register number into r5 */
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lbui r5, r0, TOPHYS(ex_reg_op);
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/* Form load_word jump table offset (lw_table + (8 * regnum)) */
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la r6, r0, TOPHYS(lw_table);
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addk r5, r5, r5;
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addk r5, r5, r5;
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addk r5, r5, r5;
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addk r5, r5, r6;
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bra r5;
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ex_lw_end: /* Exception handling of load word, ends */
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ex_sw:
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/* Get the destination register number into r5 */
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lbui r5, r0, TOPHYS(ex_reg_op);
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/* Form store_word jump table offset (sw_table + (8 * regnum)) */
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la r6, r0, TOPHYS(sw_table);
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add r5, r5, r5;
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add r5, r5, r5;
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add r5, r5, r5;
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add r5, r5, r6;
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bra r5;
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ex_sw_tail:
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mfs r6, resr;
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nop
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andi r6, r6, 0x800; /* Extract ESR[W] */
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beqi r6, ex_shw;
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/* Get the word - delay slot */
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swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
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/* Store the word, byte-by-byte into destination address */
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_0);
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sbi r3, r4, 0;
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_1);
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sbi r3, r4, 1;
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
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sbi r3, r4, 2;
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
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sbi r3, r4, 3;
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bri ex_handler_done;
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ex_shw:
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/* Store the lower half-word, byte-by-byte into destination address */
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swi r3, r0, TOPHYS(ex_tmp_data_loc_0);
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_2);
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sbi r3, r4, 0;
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lbui r3, r0, TOPHYS(ex_tmp_data_loc_3);
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sbi r3, r4, 1;
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ex_sw_end: /* Exception handling of store word, ends. */
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ex_handler_done:
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lwi r5, r1, 0 /* RMSR */
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mts rmsr, r5
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nop
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lwi r3, r1, PT_R3
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lwi r4, r1, PT_R4
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lwi r5, r1, PT_R5
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lwi r6, r1, PT_R6
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lwi r17, r1, PT_R17
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rted r17, 0
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addik r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
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.end _hw_exception_handler
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ex_handler_unhandled:
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/* FIXME add handle function for unhandled exception - dump register */
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bri 0
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.section .text
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.align 4
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lw_table:
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lw_r0: R3_TO_LWREG (0);
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lw_r1: LWREG_NOP;
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lw_r2: R3_TO_LWREG (2);
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lw_r3: R3_TO_LWREG_V (3);
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lw_r4: R3_TO_LWREG_V (4);
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lw_r5: R3_TO_LWREG_V (5);
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lw_r6: R3_TO_LWREG_V (6);
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lw_r7: R3_TO_LWREG (7);
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lw_r8: R3_TO_LWREG (8);
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lw_r9: R3_TO_LWREG (9);
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lw_r10: R3_TO_LWREG (10);
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lw_r11: R3_TO_LWREG (11);
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lw_r12: R3_TO_LWREG (12);
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lw_r13: R3_TO_LWREG (13);
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lw_r14: R3_TO_LWREG (14);
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lw_r15: R3_TO_LWREG (15);
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lw_r16: R3_TO_LWREG (16);
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lw_r17: LWREG_NOP;
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lw_r18: R3_TO_LWREG (18);
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lw_r19: R3_TO_LWREG (19);
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lw_r20: R3_TO_LWREG (20);
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lw_r21: R3_TO_LWREG (21);
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lw_r22: R3_TO_LWREG (22);
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lw_r23: R3_TO_LWREG (23);
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lw_r24: R3_TO_LWREG (24);
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lw_r25: R3_TO_LWREG (25);
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lw_r26: R3_TO_LWREG (26);
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lw_r27: R3_TO_LWREG (27);
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lw_r28: R3_TO_LWREG (28);
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lw_r29: R3_TO_LWREG (29);
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lw_r30: R3_TO_LWREG (30);
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lw_r31: R3_TO_LWREG (31);
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sw_table:
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sw_r0: SWREG_TO_R3 (0);
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sw_r1: SWREG_NOP;
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sw_r2: SWREG_TO_R3 (2);
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sw_r3: SWREG_TO_R3_V (3);
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sw_r4: SWREG_TO_R3_V (4);
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sw_r5: SWREG_TO_R3_V (5);
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sw_r6: SWREG_TO_R3_V (6);
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sw_r7: SWREG_TO_R3 (7);
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sw_r8: SWREG_TO_R3 (8);
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sw_r9: SWREG_TO_R3 (9);
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sw_r10: SWREG_TO_R3 (10);
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sw_r11: SWREG_TO_R3 (11);
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sw_r12: SWREG_TO_R3 (12);
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sw_r13: SWREG_TO_R3 (13);
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sw_r14: SWREG_TO_R3 (14);
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sw_r15: SWREG_TO_R3 (15);
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sw_r16: SWREG_TO_R3 (16);
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sw_r17: SWREG_NOP;
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sw_r18: SWREG_TO_R3 (18);
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sw_r19: SWREG_TO_R3 (19);
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sw_r20: SWREG_TO_R3 (20);
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sw_r21: SWREG_TO_R3 (21);
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sw_r22: SWREG_TO_R3 (22);
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sw_r23: SWREG_TO_R3 (23);
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sw_r24: SWREG_TO_R3 (24);
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sw_r25: SWREG_TO_R3 (25);
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sw_r26: SWREG_TO_R3 (26);
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sw_r27: SWREG_TO_R3 (27);
|
|
sw_r28: SWREG_TO_R3 (28);
|
|
sw_r29: SWREG_TO_R3 (29);
|
|
sw_r30: SWREG_TO_R3 (30);
|
|
sw_r31: SWREG_TO_R3 (31);
|
|
|
|
/* Temporary data structures used in the handler */
|
|
.section .data
|
|
.align 4
|
|
ex_tmp_data_loc_0:
|
|
.byte 0
|
|
ex_tmp_data_loc_1:
|
|
.byte 0
|
|
ex_tmp_data_loc_2:
|
|
.byte 0
|
|
ex_tmp_data_loc_3:
|
|
.byte 0
|
|
ex_reg_op:
|
|
.byte 0
|