mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 04:35:27 +07:00
dc37374b9c
It makes no sense that some Freescale device tree files are in fsl directory while some others not. This patch move Freescale device tree files into fsl folder. To do that the following two steps are made: - Move Freescale device tree files into fsl folder. - Update the include path in these files from "fsl/*.dtsi" to "*.dtsi". Please add "fsl/" prefix when you make dtb using Makefile. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> [scottwood: fixed cuImage rule] Signed-off-by: Scott Wood <scottwood@freescale.com>
448 lines
11 KiB
Plaintext
448 lines
11 KiB
Plaintext
/*
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* MPC8569E MDS Device Tree Source
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*
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* Copyright (C) 2009 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "mpc8569si-pre.dtsi"
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/ {
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model = "MPC8569EMDS";
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compatible = "fsl,MPC8569EMDS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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ethernet5 = &enet5;
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ethernet7 = &enet7;
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rapidio0 = &rio;
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};
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memory {
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device_type = "memory";
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};
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lbc: localbus@e0005000 {
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reg = <0x0 0xe0005000 0x0 0x1000>;
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ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
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0x1 0x0 0x0 0xf8000000 0x00008000
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0x2 0x0 0x0 0xf0000000 0x04000000
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0x3 0x0 0x0 0xfc000000 0x00008000
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0x4 0x0 0x0 0xf8008000 0x00008000
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0x5 0x0 0x0 0xf8010000 0x00008000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x02000000>;
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bank-width = <1>;
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device-width = <1>;
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partition@0 {
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label = "ramdisk";
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reg = <0x00000000 0x01c00000>;
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};
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partition@1c00000 {
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label = "kernel";
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reg = <0x01c00000 0x002e0000>;
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};
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partiton@1ee0000 {
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label = "dtb";
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reg = <0x01ee0000 0x00020000>;
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};
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partition@1f00000 {
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label = "firmware";
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reg = <0x01f00000 0x00080000>;
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read-only;
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};
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partition@1f80000 {
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label = "u-boot";
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reg = <0x01f80000 0x00080000>;
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read-only;
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};
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};
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bcsr@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8569mds-bcsr";
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reg = <1 0 0x8000>;
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ranges = <0 1 0 0x8000>;
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bcsr17: gpio-controller@11 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8569mds-bcsr-gpio";
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reg = <0x11 0x1>;
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gpio-controller;
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};
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};
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nand@3,0 {
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compatible = "fsl,mpc8569-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <3 0 0x8000>;
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};
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pib@4,0 {
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compatible = "fsl,mpc8569mds-pib";
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reg = <4 0 0x8000>;
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};
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pib@5,0 {
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compatible = "fsl,mpc8569mds-pib";
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reg = <5 0 0x8000>;
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};
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};
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soc: soc@e0000000 {
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ranges = <0x0 0x0 0xe0000000 0x100000>;
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i2c-sleep-nexus {
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i2c@3000 {
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rtc@68 {
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compatible = "dallas,ds1374";
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reg = <0x68>;
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interrupts = <3 1 0 0>;
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};
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};
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};
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sdhc@2e000 {
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status = "disabled";
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sdhci,1-bit-only;
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bus-width = <1>;
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};
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par_io@e0100 {
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num-ports = <7>;
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qe_pio_e: gpio-controller@80 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8569-qe-pario-bank",
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"fsl,mpc8323-qe-pario-bank";
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reg = <0x80 0x18>;
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gpio-controller;
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};
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qe_pio_f: gpio-controller@a0 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8569-qe-pario-bank",
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"fsl,mpc8323-qe-pario-bank";
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reg = <0xa0 0x18>;
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gpio-controller;
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};
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pio1: ucc_pin@01 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
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0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
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0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
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0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
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0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
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0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
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0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
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0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
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0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
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0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
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0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
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0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
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0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
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0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
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};
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pio2: ucc_pin@02 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
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0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
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0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
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0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
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0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
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0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
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0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
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0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
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0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
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0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
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0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
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0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
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0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
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0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
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};
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pio3: ucc_pin@03 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
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0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
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0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
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0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
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0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
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0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
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0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
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0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
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0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
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0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
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0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
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0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
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0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
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0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
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};
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pio4: ucc_pin@04 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
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0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
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0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
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0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
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0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
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0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
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0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
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0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
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0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
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0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
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0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
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0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
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0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
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0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
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};
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};
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};
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qe: qe@e0080000 {
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ranges = <0x0 0x0 0xe0080000 0x40000>;
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reg = <0x0 0xe0080000 0x0 0x480>;
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spi@4c0 {
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gpios = <&qe_pio_e 30 0>;
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mode = "cpu-qe";
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serial-flash@0 {
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compatible = "stm,m25p40";
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reg = <0>;
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spi-max-frequency = <25000000>;
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};
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};
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spi@500 {
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mode = "cpu";
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};
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usb@6c0 {
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fsl,fullspeed-clock = "clk5";
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fsl,lowspeed-clock = "brg10";
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gpios = <&qe_pio_f 3 0 /* USBOE */
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&qe_pio_f 4 0 /* USBTP */
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&qe_pio_f 5 0 /* USBTN */
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&qe_pio_f 6 0 /* USBRP */
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&qe_pio_f 8 0 /* USBRN */
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&bcsr17 1 0 /* SPEED */
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&bcsr17 2 0>; /* POWER */
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};
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enet0: ucc@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk12";
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pio-handle = <&pio1>;
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tbi-handle = <&tbi1>;
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phy-handle = <&qe_phy0>;
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phy-connection-type = "rgmii-id";
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};
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mdio@2120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2120 0x18>;
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compatible = "fsl,ucc-mdio";
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qe_phy0: ethernet-phy@07 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1 0 0>;
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reg = <0x7>;
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};
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qe_phy1: ethernet-phy@01 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1 0 0>;
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reg = <0x1>;
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};
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qe_phy2: ethernet-phy@02 {
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interrupt-parent = <&mpic>;
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interrupts = <3 1 0 0>;
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reg = <0x2>;
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};
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qe_phy3: ethernet-phy@03 {
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interrupt-parent = <&mpic>;
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interrupts = <4 1 0 0>;
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reg = <0x3>;
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};
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qe_phy5: ethernet-phy@04 {
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reg = <0x04>;
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};
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qe_phy7: ethernet-phy@06 {
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reg = <0x6>;
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};
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@3520 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3520 0x18>;
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compatible = "fsl,ucc-mdio";
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tbi6: tbi-phy@15 {
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reg = <0x15>;
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device_type = "tbi-phy";
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};
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};
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mdio@3720 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3720 0x38>;
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compatible = "fsl,ucc-mdio";
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tbi8: tbi-phy@17 {
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reg = <0x17>;
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device_type = "tbi-phy";
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};
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};
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enet2: ucc@2200 {
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device_type = "network";
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compatible = "ucc_geth";
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk12";
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pio-handle = <&pio3>;
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tbi-handle = <&tbi3>;
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phy-handle = <&qe_phy2>;
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phy-connection-type = "rgmii-id";
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};
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mdio@2320 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2320 0x18>;
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compatible = "fsl,ucc-mdio";
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tbi3: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet1: ucc@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk17";
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pio-handle = <&pio2>;
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tbi-handle = <&tbi2>;
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phy-handle = <&qe_phy1>;
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phy-connection-type = "rgmii-id";
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};
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mdio@3120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3120 0x18>;
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compatible = "fsl,ucc-mdio";
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet3: ucc@3200 {
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device_type = "network";
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compatible = "ucc_geth";
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk17";
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pio-handle = <&pio4>;
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tbi-handle = <&tbi4>;
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phy-handle = <&qe_phy3>;
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phy-connection-type = "rgmii-id";
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};
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mdio@3320 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3320 0x18>;
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compatible = "fsl,ucc-mdio";
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tbi4: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet5: ucc@3400 {
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device_type = "network";
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compatible = "ucc_geth";
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "none";
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tbi-handle = <&tbi6>;
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phy-handle = <&qe_phy5>;
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phy-connection-type = "sgmii";
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};
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enet7: ucc@3600 {
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device_type = "network";
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compatible = "ucc_geth";
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "none";
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tbi-handle = <&tbi8>;
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phy-handle = <&qe_phy7>;
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phy-connection-type = "sgmii";
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};
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};
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/* PCI Express */
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pci1: pcie@e000a000 {
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reg = <0x0 0xe000a000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
|
|
0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
|
|
pcie@0 {
|
|
ranges = <0x2000000 0x0 0xa0000000
|
|
0x2000000 0x0 0xa0000000
|
|
0x0 0x10000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x800000>;
|
|
};
|
|
};
|
|
|
|
rio: rapidio@e00c00000 {
|
|
reg = <0x0 0xe00c0000 0x0 0x20000>;
|
|
port1 {
|
|
ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
|
|
};
|
|
port2 {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
/include/ "mpc8569si-post.dtsi"
|