Fenghua Yu de5397ad5b x86, cpu: Enable/disable Supervisor Mode Execution Protection ... Enable/disable newly documented SMEP (Supervisor Mode Execution Protection) CPU feature in kernel. CR4.SMEP (bit 20) is 0 at power-on. If the feature is supported by CPU (X86_FEATURE_SMEP), enable SMEP by setting CR4.SMEP. New kernel option nosmep disables the feature even if the feature is supported by CPU. [ hpa: moved the call to setup_smep() until after the vendor-specific initialization; that ensures that CPUID features are unmasked. We will still run it before we have userspace (never mind uncontrolled userspace). ] Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> LKML-Reference: <1305157865-31727-1-git-send-email-fenghua.yu@intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>		2011-05-17 21:22:00 -07:00
..
cpufreq
mcheck	rcu: create new rcu_access_index() and use in mce	2011-04-01 07:27:31 -07:00
mtrr	x86, mtrr, pat: Fix one cpu getting out of sync during resume	2011-03-29 16:17:42 -07:00
.gitignore
amd.c	x86, AMD: Fix APIC timer erratum 400 affecting K8 Rev.A-E processors	2011-05-01 18:55:51 +02:00
bugs_64.c
bugs.c
centaur.c
common.c	x86, cpu: Enable/disable Supervisor Mode Execution Protection	2011-05-17 21:22:00 -07:00
cpu.h
cyrix.c
hypervisor.c
intel_cacheinfo.c
intel.c
Makefile
mkcapflags.pl
mshyperv.c
perf_event_amd.c	perf, x86: Fix AMD family 15h FPU event constraints	2011-04-19 10:07:55 +02:00
perf_event_intel_ds.c
perf_event_intel_lbr.c
perf_event_intel.c	perf events, x86: Fix Intel Nehalem and Westmere last level cache event definitions	2011-05-06 11:24:48 +02:00
perf_event_p4.c	perf, x86, nmi: Move LVT un-masking into irq handlers	2011-04-27 17:59:11 +02:00
perf_event_p6.c
perf_event.c	perf, x86, nmi: Move LVT un-masking into irq handlers	2011-04-27 17:59:11 +02:00
perfctr-watchdog.c
powerflags.c
proc.c
scattered.c
sched.c
topology.c
transmeta.c
umc.c
vmware.c